SDRAM Clock Phase Shifting Estimation

This article reprinted to: http://blog.ednchina.com/ilove314/955999/message.aspx

Quartus II handbook version 9.0 Volume 5: Section I 1 in Embedded peripherals. the SDRAM controller core section describes how to estimate the effective signal window of the SDRAM data and provides an estimation formula for the phase shifting between the SDRAM clock and the FPGA clock.

Next we will discuss the case and give some derivation and explanation of the formula officially provided. (For details, refer to the information provided above. This article focuses on the estimation formula .) The four formulas 1 and 2 in the original text are shown in.

 

Figure 1

 

Figure 2

The Derivation 3 and 4 of the above four formulas are shown in.

 

Figure 3

 

Figure 4

The four parameters obtained above are substituted into the following two formulas to obtain maximum lag and maximum lead.

Maximum Lag = Minimum (read lag, write lag)

Maximum lead = Minimum (read lead, write lead)

The final phase shifting value is obtained by (maximum lag + maximum lead)/2. A simple understanding is that the phase shift value meets the median value of the minimum valid range for Data Reading and writing.

In the past, privileged students did not have much way to estimate the phase shift. They could only find the best phase shift value by feeling, or locate the best phase shift value again and again based on the timing analysis results. The workload was heavy, there are also some components of luck, and the method officially proposed by Altera is still very effective, at least it can locate the user's phase shift value in a relatively small range and then adjust it. On this basis, we also need to consider the effects of some PLL output latencies, such as the board-level latencies, which can be done simply by fine-tuning.

In order to verify whether this estimation method is feasible in engineering applications, privileged students specially come up with some parameters of a relatively stable SDRAM Controller for calculation. Estimated parameters 5, 6, 7, and 8. Figure 5 shows the minimum r2p Output Time of slack, Figure 6 shows the maximum r2p Output Time of slack, and Figure 7 shows the time parameter for setting up the FPGA register provided by datasheet, these parameters can also be found in the path analysis report of timequest. Figure 8 shows the relevant time series parameters provided by Datasheet of SDRAM.

 

Figure 5

 

 

Figure 6

 

Figure 7

 

Figure 8

Combined with the above parameters, we can estimate the phase shift 9.

 

Figure 9

The estimated optimal phase shifting value is 1.2005ns, while the stable phase shifting in the actual project is 2ns, that is, within the fine-tuning range of the estimated value