SDRM/DDR addressing

DDR internal composition

DDR is composed of multiple storage arrays. We call these storage arrays as banks. The early SDRAM was split into two banks, and then four, this is the maximum number of banks specified in the SDRAM specification. In the DDR2 standard, the number of banks is increased to 8.

Each storage array is like a table. Each cell in a table is the smallest storage unit. The size can be 4, 8, or 16, that is, the bit width. The Bit Width determines the number of data lines. If you want to use a 32bit data bus width, you can use a single 32 bit memory chip, or use two 16 Bit Width chips to splice a 32bit.

The total capacity of the entire chip is calculated using the following formula:

Number of cells = number of rows * Number of Columns

Total capacity (unit: Bit) = number of banks * Number of cells * cell size = number of banks * number of rows * Number of columns * cell size

Taking k4b4g1646b 4gbit as an example, from its datasheet, we can see that the storage configuration is 256 MB x 16 bit, the number of banks is 8, and the row address line is a0 ~ A14, column address line a0 ~ A9

Total capacity 4 Gbit = 256 MB * 16bit = 8*32 MB * 16bit = 8*32 K * 1 K * 16bit

There are a total of 8 banks, each of which is a 32 k x 1 K cell array, each storing 16 bit data.

Chip Width

In the k4b4g1646b chip manual, the 4 Gbit capacity chip has the following three specifications: 1 GB x 4,512 GB x 8,256 GB x 16. With the same capacity, the bit width has multiple designs. The 1 GB x 4 Bit Width requires 8 chips to form a 32-bit data cable, but the total capacity can be up to 32 Gbit; if you use 1 GB x 16, you only need 2 chips to form a 32-bit data cable, the total capacity is 8 Gbit. From the above, we can see that we need to weigh the number of chips and the total capacity in the design.

How is SDRAM/DDR addressable?

To read the data of a specific cell, you must first determine which Bank to address and then perform row and column addressing in the selected bank. In practice, the Bank address and the corresponding line address are sent at the same time. In this case, this command is called "valid" or "active ". After that, send the column address addressing command and the specific operation command (read or write). These two commands are also sent at the same time. The row and column addresses can be reused. Generally, the address line of the DDR chip is a0 ~ A15, low-address lines will be reused by rows and columns. Taking the k4b4g1646b 4 Gbit 256 MB x 16bit memory chip as an example, a0 ~ A14 is used as the line address, a0 ~ A9 is used as a column address. This chip also contains B0 ~ B2 is used to select the bank.