Simple simulation process based on modelsim-se-up

A simple simulation process based on Modelsim-se to write RTL function code

To perform the function simulation, the first need to simulate the module, that is, RTL function code, referred to as the module to be tested, the module is designed to download to the FPGA circuit. One circuit module wants to have the output, must have the output, the digital circuit is also the same, the clock and the reset signal is one of the necessary test excitation signal, also may include the control signal, the data signal. To summarize, the test excitation signals included in the general system are mainly four categories:

1. System signal (clock, clock enable signal, reset signal, etc.);
2. Control signal (Enable signal, chip select signal, handshake signal, state machine control signal, etc.);
3. Data signal (parallel interface data signal, serial interface data signal, etc.);
4. Address signal (address signal of the module, internal register/memory address signal, etc.).

And for the test results, in different test excitation signal under the conditions of analysis, different test excitation to produce the corresponding test results, through the analysis can know the corresponding test results and the target results are consistent, if inconsistent with RTL modification, if consistent, modify the test excitation signal, After traversing the test excitation in different situations, complete the function test of the whole 100% to ensure the design function integrity of RTL function module.

It is important to note that functional simulation is not necessarily able to ensure that the final synthesis, layout and routing after the download to the FPGA results in the correct function, but the function of the simulation is not correct, the performance of the FPGA results must be incorrect! So the function simulation is very necessary!

This experiment needs to design a 8bit counter, the function is very simple, the counter on the rising edge of each clock plus the result output, when the count to 255 return to 0 re-count, to this cycle, the module interface is as follows.

The test excitation signal is the clock and reset signal, the clock signal is 50M, the reset signal is active low. The test result is a count value of 8bit, ranging from 0~255 to a sawtooth wave from the waveform.

Module Counter ( Class Reset_n, Counter_out ); Input CLK; Input reset_n; Output [7:0]counter_out; reg [7:0]counter_reg; Assign counter_out = Counter_reg; Always @ (Posedge CLK or Negedge reset_n) Begin if (reset_n = = 1 ' b0) Begin Counter_reg <= 8 ' D0; End Else Begin Counter_reg <= Counter_reg + 1 ' B1; End End Endmodule

Writing Testbench Code

Testbench Basic concepts: test excitation-beta RTL function module--Compare to waveform/print in terminal or produce text/auto contrast output results.

Testbench Write three-step song :

1. The top-level interface of the test design is instantiated;
2. Adding the excitation signal to the input interface of the test design;
3. Determine whether the output of the test design is intended to meet the design requirements;

testbench content is mainly divided into :

1. The generation of clocks;
2. The production of the reset;
3. The generation of control signals;
4. Generation of other excitation signals (user-defined).

The input excitation corresponding to the tested module is set to Reg type, the output is set to wire type, and bidirectional port inout is required to be processed in the test.

how to set up bidirectional port inout:

To set the intermediate variable Inout_reg for the bidirectional port inout as the output of the inout, the inout port is defined as a wire variant in Testbench, and then the output is used to control the direction of transmission.

InOut Pin_dir_port; Wire Pin_dir_port; Reg Pin_dir_port_reg; Reg Pin_dir_port_oe; Assign Pin_dir_port = Pin_dir_port_oe? Pin_dir_port_reg:1 ' BZ;

Use Pin_dir_port_oe to control the port data direction, and use the intermediate variable register to change its value, equal to two modules with inout bidirectional port interconnection.

The main testbench of this experiment is to generate a test excitation signal for the 8bit counter, that is to produce 50M clock signal CLK and reset signal reset_n.

A complete Testbench file contains three parts:

1. Simulation time Unit;
2. Module signal mapping to be tested;
3. Excitation signal generation;

Simulation Time Unit

As shown in the note: ' Timescale 1 NS/10 PS, the time unit is 1ns, the accuracy is 10PS, the time unit should be greater than the time accuracy, or the simulation process will be error, while the simulation of the time accuracy is smaller, the simulation results of the waveform of the smaller the visual accuracy, the need for simulation time requirements higher, The smaller the accuracy, the longer the simulation time.

Module signal mapping to be tested

Mapping the test function module to Testbench, shown in callout 2, is typically mapped in the following format, where the input signal of the test function module is defined as a reg signal in Testbench, because the assignment operation is performed in always. The output signal of the test function module is defined as a wire signal, which is used only for observation and not for assignment operation.

Test function module Instantiate test function module name ( Input signal (test excitation signal), Output signal (defined as wire type signal for observation) );

Excitation Signal generation

The generation of excitation signals involves two phases: the initialization phase and the assignment operation phase. The initialization phase is operated in the initial module, and the assignment operation phase is performed in the Always module, in the following format. $display is the display statement, the contents of the double quotation marks inside the parentheses are the content to be displayed, and the content will be displayed in the Script display window of the Modelsim software.

The initial module executes only once.

Initial Begin Code that executes only once Insert code here--Begin Operation of initial assignment of excitation signal --End $display ("Running testbench"); End

After the initialization is done, the excitation signal needs to be assigned to operate, the assignment is performed in always, and the Forever module is executed. The experiment clock signal is 50M, the definition of the time unit is 1ns, so in each 10ns to flip, reset signal is active low, so at the time of initialization is set to low level, in the Always module is set to High level. The format is as follows:

Always Optional Sensitivity list @ (event1 or Event2 or .... eventn) Begin Code executes for every event on sensitivity list Insert code here--Begin Excitation signal assignment operation, continuous execution --End End

Testbench Code:

' Timescale 1 NS/10 PS Module COUNTER_TST (); Constants General purpose Registers Test Vector Input Registers Reg CLK; Reg Reset_n; Wires Wire [7:0]counter_out; Counter Counter_1 ( . CLK (CLK), . Reset_n (Reset_n), . Counter_out (Counter_out) ); Initial Begin Code that executes only once Insert code here--Begin Clk<=1 ' B0; Reset_n<=1 ' B0; --End $display ("Running testbench"); End Always Optional Sensitivity list @ (event1 or Event2 or .... eventn) Begin Code executes for every event on sensitivity list Insert code here--Begin #10 clk<=~clk; Reset_n<=1 ' B1; --End End Endmodule

Create a project

Run Modelsim by clicking Start-and-click Program->modelsim Se->modelsim or double-clicking the shortcut on the desktop, which appears as shown in the interface, if the previous project was built using Modelsim, This will automatically open the last project you created, close project, select the project file, right-click, and select Close project in the column that appears.

Click on File->new->project and the interface shown will appear.

After you select project, the following interface appears in Project name, we enter the project name as counter, click the Browse button in project location, select the path to save the project, and note Modelsim It is not possible to automatically create a directory for a project, it is best to choose a project folder that has been created as a directory, in the default library Name for our design to which library, the use of the defaults, so that after compiling the design file, in the Workspace window Work library will appear in the library. When we have finished typing here, click OK.

Click on the OK button will appear to select the simulation file interface, as shown, you can click on different icons to add different projects for the project, click Create New file to add new files for the project, click Add Existing file for the project to add the existing files, click Create Simulation to add a simulation to the project, click Create New folder to add the catalog to the project. Here we click Add Existing File;

here the counter.v file and the COUNTER_TST.V file are included in the project, click the Browse button to include the file, as shown in, and then click the OK button.

It will then appear as shown in the Project work window of Modelsim, where two files have been included, with two question marks appearing in the State column indicating that the file was included and not compiled.

Simple simulation process based on modelsim-se-up