Software design of SOPC system custom Peripherals

Source: Internet
Author: User

After you complete the hardware design of the custom peripherals, you need to write software to test the design of the peripherals.

Before that, you have to figure out the address alignment in Nios II, for Avalon Slave, there are two kinds of address alignment: Dynamic address alignment and static address alignment.

Dynamic address alignment: Dynamic address alignment can automatically accommodate devices with different Avalon master port widths while maintaining address growth in bytes. Use dynamic address alignment to get a contiguous memory space when master and slave match different port widths. However, dynamic address alignment has a role in reading operations. When a 32-bit Nios II Core reads a 8-bit wide slave, Physics produces 4 8-bit read operations, while reading a 16-bit-wide slave produces 2 read operations. Most register types of peripherals do not tolerate this attachment, so dynamic address alignment is generally not suitable for register peripherals, mainly for memory. If the width of the external memory is greater than 8 bits, such as 16-bit or 32-bit, there must be a byte-enabled signal for the byte-granularity write operation. So in the interface for these memory, if the use of dynamic address alignment, you must connect byte enabling signal.

Static address alignment: Static address-aligned address growth unit is the port width of Avalon Master, and each read-write only corresponds to a single operation does not have any effect. However, when you match master and slave with different port widths, the addresses are not automatically adjusted, and some addresses do not have corresponding physical entities and correspond to them. When a 32-bit Nios II Core reads a 8-bit-wide slave, its 32-bit data is obtained at a lower 8 bit from slave, while a high 24-bit is undefined. Similarly, when it reads a 16-wide slave, its 32-bit data gets a low 16-bit from slave, while a high 16-bit is undefined. When the Nios II Core wants to continue reading the next 8-bit (or 16-bit), it needs to grow byte address 4. Unless you need a contiguous address space, using static address alignment is a relatively safe way to do this.

During the first debugging encounter such a problem: with Iowr (keyboard_base,2,0), clear IRQ interrupt signal, in the SIGNALTAP II Logic Analyzer always catch the write signal, has been kept low level, later with IOWR (keyboard_base , 0,0) will be able to catch the write signal. I think it must be the problem of address alignment, then open Sopc Builder, ready to address alignment, but never see that item, the previous 6.0 version has this option. Toss me a day, and then had to bite the bullet to see Altera official documents, finally found the answer.

So I decided to find the source file, change the code, in the generated KEY_HW.TCL

#set_interface_property avalon_slave addressAlignment DYNAMIC

set_interface_property avalon_slave addressAlignment NATIVE

Comment out dynamic, change to native.

Recompile, the problem is not there, with Signaltap II success to capture write signal

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