Solutions to questions about CPU addressing

Today, I asked a question on the csdn compilation forum. I have been confused about CPU addressing for a few days. Now I understand it a little bit. I will continue to digest it later. I posted it to share it with you. From http://fixopen.javaeye.com/blog/27866

Why does 16-bit CPU address bus require 20

* Origin

When learning about memory addressing, most of the materials are written: To meet the 8086 M addressing space, Intel's smart engineers have come up with a "segmented" approach, to divide a 1 m space into 64 K segment address space for management, it also appears the so-called segment address + segment offset to achieve addressing purpose. The reason for this seems to be appropriate, and it is indeed very beautiful. However, with the advent of the 32-bit machine era and even the emergence of 64-bit machines, this architecture is always facing the pain of backward compatibility and needs to be "compatible.

 

But my question is: why is there a 8086 M addressing space? Isn't 64 K address space enough? Rather than "forcing" everyone to come up with "stages" such a "terrible" historical result. I do not know the real mode and protection mode that will be caused later.

 

After "google", find a reason that can barely be explained:

 

Original article address:Http://blog.chinaunix.net/u/21948/showart_239664.html

 

"But after the upgrade to a 16-bit server, the design of intel8086/8088cpu cannot exceed 40 pins due to the current icintegration technology and external encapsulation and PIN technology limitations. However, the original address addressing capacity of the 8-bit host is 2 ^ 16 = 64 KB, which is too small, but the direct increase to an integer multiple of 16 means that AB = 32 bits cannot be reached. Therefore, we can only temporarily add four AB entries to 20. The addressing capability of 2 ^ 20 = 1 MB has increased by 16 times. However, this caused a conflict between the 20-bit AB address and the 16-bit dB address. The 20-bit address information cannot be transmitted on the DB, it cannot be stored in 16-bit CPU registers and memory units. As a result, the CPU segment structure was created ."

 

Here is a reasonable reason: 40 pin limitations. Let's take a look at what 8086 looks like.

 

 

Find the datasheet of 8086 and find its pin definition:

We can see that ad0 ~ Ad15 is a time-sharing 16 bus. This results in the expectation that the addressing can be as large as possible on this basis, one of the Optional options is to use 16-bit register + 16-bit intra-segment displacement to achieve the largest and relatively simple addressing mode.

Generation of segmentation problems:

The x86 series CPU is the first 8086 series and subsequent products produced by Intel, including the products copied by various CPU manufacturers. However, it does not include subsequent 64-bit CPUs in various forms.
Segment is a storage concept.
What is described below is my imagination. You can regard it as a romance. :). You don't have to take it seriously.
Intel's CPU has been 16 bits since 8086. The so-called 16-bit refers to its data bus and address bus. (Note that the address bus is not so. It will be explained in detail later. In fact, its address bus is 20 bits), each register is 16 bits width. That's a simple age. A 16-bit address bus can address 64 KB of address space. Even in that age, 64 K was a little small. Therefore, Intel decided to use the 20-bit address bus (in line with IBM's requirements. But this raises a problem: how to set the instruction set? You know, 20-bit is four more places than 16-bit. Where are these four places? Registers are all 16 bits! Intelligent intel engineers began to think of a way (I guess it was inspired by DEC that its CPU is segmented memory. However, Intel's segments are quite different from him, DEC does not overlap segments, while Intel segments can overlap). It divides the address space into two parts. One part is called the segment base address and the other part is called the intra-segment address. The intra-segment address is the original 16-bit address, so the maximum segment size is 64 K. What should I do with the base segment address? We know that the base address of a segment must represent an address in a 20-bit address space (that is, a 1 M address space). The most reasonable choice is 20. However, Intel engineers thought that it was unreasonable to place a 20-bit register in a 16-bit CPU, so they adopted a clever method of laziness. A 16-bit register is used to express a 20-bit address with four low bits and zero bits. To be clear, I use hexadecimal notation to represent a 16-bit register with the value of NNNN, so we can regard it as an address like nnnn0. This is the base address register. It is simply called a segment register. When we want to access any address area in the 1 m address space, we can adjust the value of the segment register to be close (the so-called proximity, that is, smaller than the address space, but not less than 64 KB). Then, you can access any address space within 1 MB by the sum of the base address and the intra-segment address. This operation is called segment switching. The segment length is still 16 bits, which also limits the segment length to 64 K. Here, you may think of something and may recall the so-called near pointer and remote pointer. Haha. After the mechanism is described, let's take a look at some interesting restrictions and problems caused by this design. First, the segment base address is limited to 4 low bits to 0, that is, the form of nnnnnn0, so the segment base address must be an integer multiple of 16. Haha, this 16 is called para (paragraph, segment! Note that the segment we described above is called the segment by Intel engineers ). Secondly, because the address of ffff0 + FFFF addressing is already larger than 1 m (in fact, a whole segment length is larger than 1 m, 64 K ), in fact, the 20-bit address bus can only address 1 m of address space. This shows that our intel engineer's design is not up to standard! Well, I did not expect such a problem. Later, it should be an Intel guy with a slightly abnormal psychology: Let's let him go back. At the beginning, it was estimated that everyone thought it was a failure. Later, everyone was amused by this idea, and the loop was confirmed. Let me talk about the loop. Very interesting. Because the base address of a CIDR block + the address in the CIDR block can express an address space of more than 1 MB, and the address bus can only address 1 MB, all addresses that exceed 1 MB of the CIDR block are equal to 1 MB. That is to say, all the address spaces larger than 1 MB are re-calculated from 0, as if they were re-taken. This is the loop.
Is there 5 internal 8086cpu? Segment registers. That is to say, we can maintain the existence of five segments at the same time. If we need more than five segments, you can switch the segments.
This is the origin of the paragraph.
Because 80186 failed, and there was little information available, I did not say it, 80286 came out. She introduced protection for the first time. As we can use the memory segments, it seems that we can also specify the right to a specific segment. For example, a text segment can only be executed, or an RDATA segment can only be read. Therefore, it seems logical to add protection to the initial segment mechanism. However, 286 does not have much to consider when it comes to protection, so it is not perfect.
Let's analyze it carefully. Because the segment is specified at the Para boundary. At the same time, we can specify a segment on the boundary of Para and emphasize that Para is 16. This indicates that the difference between the two base addresses can be at least 16. The maximum length of a segment can be 64 K. What does this cause? This causes overlapping segments. That is to say, the address of a real address space can belong to multiple segments at the same time. So what does our protection look like? What is the total accessibility of all segments? Minimum accessibility? There is no conclusion. Therefore, the protection of buckets through segments is not very smooth in Intel's CPU (I do not want to deny segment protection, on the contrary, the complete segment protection mechanism is very useful, unfortunately, it won't work on x86 machines ). On x86 machines, we lack some things. We generally think that we must add segments and prohibit overlapping segments to implement segment protection. Of course, 286 has indeed implemented some protection, so the 286 segment switching costs more than 8086. The reason is that there are more scenarios to be switched during segment switching.
The descriptions above are not facts, or at least some are not facts. That is: the segment register in section 286 is no longer a simple segment base address. It stores something called a segment selection sub-item, which points to an item in the segment descriptor table in the bucket, or simply points to the segment descriptor. What is stored in the segment descriptor is the real segment base address or something. In straightforward terms, we say it introduces an indirect method.
When 386 came out, we saw that the addressing space and OS of other CPUs were expanding rapidly. Intel finally developed a 32-bit CPU. The 32-bit address space can logically address 4G storage systems. Simply put, we can think that the segment address is expanded to 32 bits, but the concept and implementation method of the segment are not much different from those of 286. 386 introduced the concept of a page, but this is irrelevant to our topic.
Let's talk about the development of OS. The physical memory is not scaled in proportion due to the expanded address space. (Note: The number of 16 bits is expanded to 32 bits, and the address space is increased to 65536 times. Even if the number of 20 bits is increased to 32 bits, the address space is increased by 4096 times ). The physical space is increased by about 500 times. There is a huge difference between them. Smart people come up with something called virtual memory. Try to use the address space as much as possible. The basic strategy is to pretend to be memory with a portion of the hard disk (or other external storage devices. What are the benefits of doing so? Starting from the features of a program, it is impossible for a program to access all the data in the address space at the same time. Instead, it is concentrated in a region for a period of time. This feature is called locality. According to the locality, If you need immediate access in the physical memory, you do not need immediate access in the virtual memory. When you need access, you can load it into the memory for access. This simplifies the application logic, and the application only needs to use all the address space according to its own intention. The switching between physical memory and virtual memory is completed by the OS. Implementing virtual memory requires the support of the CPU (in fact, if not, but the performance cannot be guaranteed at all). Currently, the only common method is memory paging, this reset process is also called a page change. Logically, we can use segments to Implement Virtual Memory (think about the segment switching mentioned above). However, due to segment irregularities (the page size is consistent and regular, but the segment is not, see the previous description), the implementation is relatively complex, requires more CPU support, performance is more difficult to guarantee. Therefore, modern operating systems all use pagination instead of segmented storage.
So what about the OS for x86 CPUs that support segments and paging? In fact, it's easy to simply ignore segments. That said, it's not something you want to ignore. When x86cpu accesses the bucket address, it uses the segment base address + intra-segment address. This is the hardware implementation. can we ignore it? What if we set the base address to 0? In this way, we can ignore segments. Yes, modern OS does this.
For example, in windows, several segment registers (where the segment is selected) point to the 28 (as if it is) segment descriptor, while the 28 segment descriptor is of the 0 base address.
Speaking of the same level, the x86 series CPU segment mechanism is quite well designed and has a baroque taste, just like Intel's first 64-bit CPU attempt at anteng. Haha.
Everything above is a memory. without providing any guarantee of correctness, smart people will not look at it. Of course, people who read it are smarter.