Some trivial knowledge of FPGA finishing

1. Manufacturers of FPGA production are:

ALTERA

XILINX

Atcel

Lattice

Ps:

Altera and Xilinx mainly produce FPGA for general purpose, whose main products are SRAM process

Actel mainly provides non-volatile FPGA, the product is mainly based on the anti-fuse process and flash process

　　　　　　　　　　PS: Fuse, as the name implies: Melt the wire off, reverse fuse technology on the contrary, the original broken point in the burning, short-connected, this short-term is permanent!

　　　　　　　　　　　　Anti-FUSE is disposable!!　

2.FPGA is stored in the on-chip RAM program to set its working state , the work needs to program the on-chip RAM, when the power-down FPGA into a white chip !!

Since the LUT is mainly suitable for the production of SRAM technology, so at present most of the FPGA is based on the SRAM process, and the SRAM technology chip in the power loss after the information will be lost, it is necessary to add a special configuration chip, in power, by this special configuration chip to load the data into the FPGA, Then the FPGA will work properly, because the configuration time is very short, will not affect the system to work properly.

There are different programmatic configuration methods for this:

Parallel main mode for a piece of FPGA to add an EPROM way;

Master-Slave mode can support a piece of prom programming multi-chip FPGA;

Serial prom can be used to program FPGA.

The peripheral mode allows the FPGA to be used as a peripheral to the microprocessor and programmed by the microprocessor.

Identification and classification of 3.FPGA and CPLD:

The device which constructs the logical behavior by the product item structure is called CPLD.

A device that constructs a logical behavior by looking up a table method is called an FPGA.

4.FPGA internal three basic resources:

CLB Programmable logic function block, IOB programmable output input block, programmable internal interconnect resources.

5.FPGA ways to Implement features:

PLD/FPGA development software automatically calculates all the possible results of a logical circuit and writes the result in advance to ram, so that each input signal is logically calculated to enter an address to look up the table, find the address corresponding to the content, and then output.

The a,b,c,d is entered into a programmable connection by the pin of the FPGA chip, and then connected to the Lut,lut as the address line has written all possible logical results in advance, through the address to find the corresponding data and then output, so that the combined logic is implemented.

1 Labs consist of 8 LE (minimum logical units), and one le is composed mainly of registers and Lut. (look-up-table)

A logical unit consists mainly of the following components: a four-input query table (lookup Table,lut), a programmable register, a carry chain, and a register-level chain.

Lut essentially is a 16bit SRAM (static random memory), 4 input is actually the address of the SRAM. is actually equivalent to a truth table. (16bit=24, 2 possibilities per input, i.e. 2*2*2*2=16)

static RAM (SRAM) is very fast and does not automatically disappear as long as the contents of the power supply are present. The basic storage circuit is composed of 6 mos tubes and 1 bits, so the integration is relatively low and the power consumption is larger . The general buffer memory is made up of it. The content of dynamic RAM (DRAM) disappears automatically after 3 or L0-6 seconds, so it must be refreshed periodically before the content disappears. Because its basic storage circuitry consists of a transistor and a capacitor, it has a high level of integration, lower cost, and less power consumption , but it requires an additional refresh circuit.

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Some trivial knowledge of FPGA finishing