Some Understandings of SDRAM and processor addressing

Author: Tian kaiwen
Date: 2011-6-6 14:59:16
PS: I will summarize it for future reference. If it is reproduced, please indicate the source
QQ: 1324343063

 

Recently, we have analyzed the cpu_init.s of 6410 in uboot. This is the configuration of DDR. Because DDR is an update of SDRAM, we will first look at the SDRAM. The following is a recent summary.

See:

 

 

 

This is 64 m (32 m + 32 m), the principle of SDRAM

1. Why does the address line 2440 or 2410 start to be connected from addr2?

The address lines in 2440 or 2410 are connected from addr2, that is, A0-ADDR2, An-ADDR (n + 2) this is because arm is a 32-bit processor, so it processes data at a time in 32-bit units, that is, when it reads or writes data, the address can only be 0x0, 0x04, 0x08, or ,... That is, 4-byte alignment. Generally, the data lines of the DDR are 16 bits. Therefore, to obtain 32 bits of data, the two ddrs are usually connected together. Their addresses include the same as those of the slices, therefore, for DDR, a single address corresponds to four bytes (because a DDR corresponds to two bytes, two ddrs correspond to four bytes ), however, for the CPU, an address corresponds to only one byte. Here there is an address conversion problem, that is, the CPU 0 ~ 3. The data in the address corresponds to the 0 address data of the DDR, and the 4-to-4 of the CPU ~ 7. The data of the address corresponds to the data of the 1 Address of the DDR. Therefore, the 0 address of the CPU corresponds to the 0 address of the DDR, the 0 address corresponds to the 1 address in the DDR, and the 0 address corresponds to the 2 address in the DDR, it can be seen that the address of the DDR is just two places to the right of the CPU addressing, so the address lines in 2440 or 2410 are connected from addr2.

 

 

 

 

 

 

2. Why does 32 m only use 13 address lines?

The first thing we need to know about the dram structure is the internal structure of DRAM:

We can see that a dram is actually composed of four 4mx16 storage blocks, that is, the bank. 4 m Refers to 4 Mbit storage units, and 16 refers to the number of storage units, 2 bytes. It can be seen that bank0 and bank1 are used to select which bank to access. In k4s561632c, there are four banks, 00 stands for bank0, 01 stands for bank1, 10 stands for bank2, and 11 stands for bank3, you need to know that these four storage blocks are independent of each other, and each bank is an array structure. The so-called array structure refers to the structure composed of rows and columns. For more information, see:

We can regard a bank as a storage block consisting of many squares, and the number of squares is 4 Mbit, and the size of each square is 16 bit, if you want to determine the address of a square, you must first determine its row address, and then its column address. The intersection of the two lines determines the address you want.

Generally, the address line of SDRAM adopts the principle of time-sharing, that is, the first line address, and then the column address. The k4s561632c chip row address: ra0 ~ Ra12, column address: Ca 0 ~ Ca8, that is, the first nine address lines are reused by the row and column.

Therefore, when addressing, send the Bank address and ra0 ~ Ra12 line address, and then send Ca 0 ~ Ca8 column address. 13 line addresses, 9 column addresses, total capacity 4*2 ^ 13*2 ^ 9 * (16/8) = 32 MB

 

3. Why is bank0 and bank1 connected to 2440 addr24 and addr25?

We have learned that bank0 and bank1 are used to select a storage block (bank). The 32 m space requires 25 address lines for addressing, but for k4s561632c, only 24 are needed, because each storage unit stores two bytes, let's split the first 13 row addresses of the 24 address lines, followed by nine column addresses, so what are the last two? Obviously, it is a bank address, which is used to select a storage block. Therefore, bank0 is connected to 23 and bank1 is connected to 24. However, we have explained the reason for the connection from addr2, therefore, add 2 for each address. the last address connection method is addr2 ~ Addr14 corresponds to the row address, addr15 ~
Addr23 corresponds to the column address (because the time-sharing of pins is actually DDR2 ~ Addr14 corresponds to the row address, addr2 ~ Addr10 corresponds to the column address) addr24 ~ Addr25 corresponds to bank0 ~ Bank1, Which is why bank0 and bank1 are connected to addr24 and addr25 of 2440.

 

 

Supplement: we can see that the figure above is composed of two k4s561632c components. What is the result of this operation?

We already know that one k4s561632c has four banks, and two k4s561632c has eight banks. When a k4s561632c is connected, one address corresponds to two bytes, and now two k4s561632c are connected, an address corresponds to four bytes, that is, a word, a total of 64 mb. When an address stores one byte, we need 64 Mbit addresses to achieve 64 MB of capacity. The current capacity remains unchanged, the number of bytes stored in each address increases, so the number of required addresses is reduced. Based on the storage capacity (byte) = number of addresses * The number of bytes that each address can store, we can see that when the number of bytes stored in each address increases by 4 times, the number of our addresses will change to the original 1/4,
When an address contains 4 bytes, we only need 16 Mbit addresses to achieve 64 MB capacity, 16 Mbit represents 24 address lines (2 ^ 24 = 16 Mbit = 16*1024*1024), but for 2440, an address can only correspond to one byte, it is measured in bytes. For example, if you define an array and initialize it: uchar A [] = {0, 1, 2, 3}; assume that 0 is stored at address, then 1 is stored in a + 1, 2 is stored in a + 2, and 3 is stored in a + 3. That is to say, for 2440, each address stores only one byte ,, therefore, for 2440, 64 MB memory requires 26 address lines. If we store these 4 bytes in the above SDRAM, they are all stored in one address, 0 and 1 are stored in k4s561632c on the left, 2 and 3 are stored in k4s561632c on the right, with the same address, it can be seen that 26 lines are used for 2440 addressing 64 MB of SDRAM (the maximum two digits are exactly 25 ~ 24 confirmed the problem 3), but the 64 mb sdram actually only needs 24 lines to be searched (because the four addresses in 2440 are equivalent to one address in SDRAM ), therefore, the last two address lines in MySQL 2440 are useless (problem 1 is confirmed ).

 

Y (^_^) y