Stack operations for task switching

OSCTXSW
                                                                  ; SAVE current TASK ' S CONTEXT:
    stmfd   sp!, {lr}                                            ;      Push return address,

; The STMFD command is a full stack decrement, that is, the instruction Stmdb (the address first minus the stack) after the content in the LR is pressed into the SP minus 1 points to the position of the
    stmfd   sp!, {lr}                                              Ibid.
    stmfd   sp!, {r0-r12}                                        ;      Push Registers,

MRS R0, CPSR; Push current CPSR,
TST LR, #1; If called from Thumb mode,
Orrne R0, R0, #OS_CPU_ARM_CONTROL_THUMB; If Yes, set the t-bit.
Stmfd sp!, {R0}

At the end of the stack, the contents of the stack are stored as follows

; Address content

; 1234	,
, 1230	LR
; 1226	LR
; 1222	R12
; 1218	R11
; 1214	R10
; 1210	R9
; 1206	R8
; 1202	R7
; 1198	R6
; 1194	R5
; 1190	R4
; 1186	R3
; 1182	R2
; 1178	R1
; 1174	R0
; 1170	CPSR

LDR R0, __os_tcbcur; Ostcbcur->ostcbstkptr = SP;
LDR R1, [R0]
STR SP, [R1]

LDR R0, __os_taskswhook; Ostaskswhook ();
MOV LR, PC
BX R0

    ldr     R0, __os_priocur                                     ; Ospriocur = Ospriohighrdy;
    ldr     R1, __os_priohighrdy
    ldrb     R2, [R1]
    strb    R2, [R0]

LDR R0, __os_tcbcur; Ostcbcur = Ostcbhighrdy;
LDR R1, __os_tcbhighrdy
LDR R2, [R1]
STR R2, [R0]

LDR SP, [R2]; SP = ostcbhighrdy->ostcbstkptr;

                                                                  ; RESTORE NEW TASK ' S CONTEXT:
    ldmfd   sp!, {r0}                                            ;     Pop New Task ' s CPSR,
    msr     spsr_cxsf, R0

Ldmfd sp!, {r0-r12, LR, pc}^; Pop New task ' s context.

The stack command LDMFD, although called full stack decrement, but the actual invocation of the instruction is ldmia, that is, the first out of the stack after the address plus 1

; The result after the stack operation

/tr> td>;1222

; address
; 1234
, 1230	PC
; 1226	LR
R12
, 1218	R11
; 1214	R10
; 1210	R9
; 1206	R8
; 1202	R7
; 1198	R6
; 1194	R5
; 1190	R4
; 1186	R3
; 1182	R2
; 1178	R1
; 1174	R0
; 1170	CPSR

PS: There is a convention, low-numbered registers in the storage of data or load data corresponding to the low address of the memory

msr{< Condition Code >cpsr_f| spsr_f,< #ommed_8r >
msr{< Condition Code >cpsr_<field>| Spsr_<field>,rm
which
The <field> field can be one or more of the following:
C: Control domain masking field (No. 0 to 7th digits in PSR);
X: Extended Domain masking field (8th to 15th in PSR);
S: State field Masking field (16th to 32nd in PSR);
F: Flag Field Screen field (24th to 31st Digit in PSR).