Stm32 24c02 function I2C routine non-stm32 library mode

# Define addr_24cxx 0xa0
Void i2c_24cxx_write (2010naddr, u8 * pdat, 2010nlen)
{
2010i = 0;
/* Enable i2c1 acknowledgement if it is already disabled by other function */
// I2c_acknowledgeconfig (i2c1, enable );
Pai_i2c1_regs-> cr1.bit. ACK = 1; // ack: response enabling 1: returns a response (matching address or data) after receiving a byte)
 
/* Send i2c1 start condition */
// I2c_generatestart (i2c1, enable );
Export _i2c1_regs-> cr1.all | = i2c_en | i2c_start;

/* Test on i2c1 ev5 and clear it */
// [SB = 1 start condition has been sent read SR1, then write data Dr cleared] MSL = "1 Main Mode" busy = "1" is performing data communication on the bus)
// While (! I2c_checkevent (i2c1, i2c_event_master_mode_select) {;}/* ev5 */
While (! (Performance_i2c1_regs-> sr1.bit. SB & i2c_sb ));

/* Send slave address for write */
// I2c_send7bitaddress (i2c1, addr_24cxx, i2c_direction_transmitter );
Pai_i2c1_regs-> dr. Bit. DR = addr_24cxx;

/* Test on i2c1 ev6 and clear it */
// [ADDR = 1 address sending ends; read SR1 and Sr2 to clear ]. Txe = "1" data register empty MSL = "1" busy = "1", tra = "1" data sent
// While (! I2c_checkevent (i2c1, i2c_event_master_transmitter_mode_selected) {;}/* ev6 */
While (! (Performance_i2c1_regs-> sr1.all & i2c_addr ));
Performance_i2c1_regs-> sr2.all;

/* Send the low part of memory address */
// I2c_senddata (i2c1, (u8) naddr );
Pai_i2c1_regs-> dr. Bit. DR = (u8) naddr;

/* Test on i2c1 ev8 and clear it */
// [Txe = 1 data register empty; write data Dr clear, start, stop] BTF = "1: "Byte sending ends tra =" data sent "busy =" data communication is ongoing on the bus "MSL =" master mode"
// While (! I2c_checkevent (i2c1, i2c_event_master_byte_transmitted) {}/* ev8 */
While (! (Performance_i2c1_regs-> sr1.all & i2c_txe ));
 
For (I = 0; I <nlen; I ++)
{
/* Send i2c1 data */
// I2c_senddata (i2c1, pdat [I]);
Pai_i2c1_regs-> dr. Bit. DR = pdat [I];

/* Test on i2c1 ev8 and clear it */
// [Txe = 1 data register empty; write data Dr clear, start, stop] BTF = "1: "Byte sending ends tra =" data sent "busy =" data communication is ongoing on the bus "MSL =" master mode"
// While (! I2c_checkevent (i2c1, i2c_event_master_byte_transmitted) {;}/* ev8 */
While (! (Performance_i2c1_regs-> sr1.all & i2c_txe ));
 
}
/* Send i2c1 stop condition */
// I2c_generatestop (i2c1, enable );
Export _i2c1_regs-> cr1.all | = i2c_en | i2c_stop;
While (pai_i2c1_regs-> sr2.bit. MSL); // 0: Slave Mode

} // End sub

// ================================================ ========================================================
//
// ================================================ ========================================================
Void i2c_24cxx_read (2010naddr, u8 * pdat, 2010nlen)
{
2010i = 0;
/* Enable i2c1 acknowledgement if it is already disabled by other function */
// I2c_acknowledgeconfig (i2c1, enable );
Pai_i2c1_regs-> cr1.bit. ACK = 1; // ack: response enabling 1: returns a response (matching address or data) after receiving a byte)
 
/* Send i2c1 start condition */
// I2c_generatestart (i2c1, enable );
Export _i2c1_regs-> cr1.all | = i2c_en | i2c_start;
 
/* Test on i2c1 ev5 and clear it */
// [SB = 1 start condition has been sent read SR1, then write data Dr cleared] MSL = "1 Main Mode" busy = "1" is performing data communication on the bus)
// While (! I2c_checkevent (i2c1, i2c_event_master_mode_select) {;}/* ev5 */
While (! (Performance_i2c1_regs-> sr1.bit. SB & i2c_sb ));
 
/* Send 24cxx slave address for write */
// I2c_send7bitaddress (i2c1, addr_24cxx, i2c_direction_transmitter );
Pai_i2c1_regs-> dr. Bit. DR = addr_24cxx;

/* Test on i2c1 ev6 and clear it */
// [ADDR = 1 address sending ends; read SR1 and Sr2 to clear ]. Txe = "1" data register empty MSL = "1" busy = "1", tra = "1" data sent
// While (! I2c_checkevent (i2c1, i2c_event_master_transmitter_mode_selected) {;}/* ev6 */
While (! (Performance_i2c1_regs-> sr1.all & i2c_addr ));
Performance_i2c1_regs-> sr2.all;
 
/* Send the low part of memory address */
// I2c_senddata (i2c1, (u8) naddr );
Pai_i2c1_regs-> dr. Bit. DR = (u8) naddr;

/* Test on i2c1 ev8 and clear it */
// [Txe = 1 data register empty; write data Dr clear, start, stop] BTF = "1: "Byte sending ends tra =" data sent "busy =" data communication is ongoing on the bus "MSL =" master mode"
// While (! I2c_checkevent (i2c1, i2c_event_master_byte_transmitted) {}/* ev8 */
While (! (Performance_i2c1_regs-> sr1.all & i2c_txe ));
 
// ================================================ ====================================
// I2c_generatestart (i2c1, enable );
Export _i2c1_regs-> cr1.all | = i2c_en | i2c_start;
 
/* Test on ev5 and clear it */
// [SB = 1 start condition has been sent read SR1, then write data Dr cleared] MSL = "1 Main Mode" busy = "1" is performing data communication on the bus)
// While (! I2c_checkevent (i2c1, i2c_event_master_mode_select) {;}/* ev5 */
 
While (! (Performance_i2c1_regs-> sr1.bit. SB & i2c_sb ));
 
/* Send 24cxx slave address for read */
// I2c_send7bitaddress (i2c1, addr_24cxx, i2c_direction_receiver );
Pai_i2c1_regs-> dr. Bit. DR = (u8) addr_24cxx | (u8) 0x01 );

/* Test on ev6 and clear it */
// [ADDR = 1 address sending ends; read SR1 and Sr2 to clear ]. Txe = "1" data register empty MSL = "1" busy = "1", tra = "1" data sent
// While (! I2c_checkevent (i2c1, i2c_event_master_receiver_mode_selected) {;}/* ev6 */
 
While (! (Performance_i2c1_regs-> sr1.all & i2c_addr ));
Performance_i2c1_regs-> sr2.all;
 
For (I = 0; I <nlen; I ++)
{
If (I + 1)> = nlen)
{
/* Disable i2c1 acknowledgement */
// I2c_acknowledgeconfig (i2c1, disable );
Export _i2c1_regs-> cr1.bit. ACK = 0; // ack: Enable closing of the response
 
/* Send i2c1 stop condition */
// I2c_generatestop (i2c1, enable );
Export _i2c1_regs-> cr1.all | = i2c_en | i2c_stop;
While (pai_i2c1_regs-> sr2.bit. MSL); // 0: Slave Mode
 
}
/* Test on ev7 and clear it */
// [Rxne = 1 data register is not empty; read/write Dr is cleared] busy = "1" Data Communication in MSL = "1" Main Mode on the bus
// While (! I2c_checkevent (i2c1, i2c_event_master_byte_received) {;}/* ev7 */
While (! (Performance_i2c1_regs-> sr1.all & i2c_rxne ));
 
/* Store i2c1 received data */
// Pdat [I] = i2c_receivedata (i2c1 );
Pdat [I] = pai_i2c1_regs-> dr. Bit. Dr;
}

} // End sub