I saw the main peripherals and circuit design of STM32 a few days ago. Today I started to see the program design of STM32.
Here I use STM32 library v3.5 directly. I'm too lazy to see any registers
The first problem encountered is the internal bus AHB and APB of STM32. Here, I check some information and record it
AMBA
AMBA (advanced microprocessorbus Architecture) is an open SoC Bus standard proposed by arm company, which has been widely used in RISC kernel.
AMBA defines a multi level bus system, including system bus and peripheral bus with lower level.
AMBA supports 32-bit, 64 bit, 128 bit data bus and 32-bit address bus, and supports byte and half word design.
It defines two kinds of buses: AHB (advanced high performance bus) advanced high performance bus, also called ASB (advanced system bus). APB (advanced peripheral bus)
AHB and ASB are actually one thing, high-speed bus, mainly responsible for the interface of embedded processor, DMA controller, memory, etc.
APB is a low-speed bus, mainly responsible for peripheral interface
AHB and APB are linked by bridge
Bus Bridges
As we all know, each module in a system communicates with each other through the bus. The function of the bus is to transfer data and address from device a to device B,
If device a and device B have consistency (the original is under discussion, I don't know how to translate it better here, let's just translate it into consistency for now), then device a and device B can directly hang on the same bus, and directly interpret the data on the bus.
However, if device a and device B do not have consistency, then device a and device B must be hung on two different buses. At this time, we need a "translation" to convert the data and address on the bus on device a into a format that can be parsed by device B, and then put it on the bus of device B. the "translation" is "bus bridge",
The figure below illustrates the role of bus bridge between AHB and APB.
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Here we can see that AHB is mainly linked to the system kernel and storage management, and APB is mainly distributed to my peripheral devices.
In the following figure, it is easier to see the role of AHB and APB: AHB links system bus, ram, etc. APB links common peripherals: GPIO, UART, etc\
Bus structure on stm32
First, let's look at the bus structure of F103 series chips
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It should be noted that there are two APBs here, and their linked peripherals are different, so there will be definitions of apb1 and apb2 in the library file of STM32:
/** @defgroup APB2_peripheral
* *
* /
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
* *
* *
* /
/** @defgroup APB1_peripheral
* *
* /
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
* *
* *
* /
The rate of APB is described below:\
Apb1 is limited to 36MHz, and apb2 can reach full speed 72mhz
Here is the bus architecture of F105 and F107:
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Address mapping of apb1 and apb2 on stm32
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