STM32 's Clock

1. Clock source

Three different clock sources can do the system clock (SYSCLK):

HSI oscillator Clock: high-speed internal clock
HSE oscillator Clock: high-speed external clock
PLL Clock

Two x two-level clocks

LSI (Low speed internal clock): 32kHz low-speed internal RC (LSI RC) Independent watchdog clock Source, RTC can be used for automatic wake-up stop/Standby mode.
LSE (Low Speed external clock): 32.768kHz Low SPEED external oscillator (LSE crystal), selectable as RTC (RTCCLK) Clock source

Each clock source can be selectively switched off when not needed to conserve system power consumption

The prescaler is used to set the AHB, APB (APB2) and APB (APB1) frequencies. The AHB domain maximum frequency can be set to 168 MHz. The APB2 domain has a maximum frequency of up to up to MHz. The APB1 domain has a maximum frequency of up to.

AHB: Mainly used to control USB, network card, IO port, DMA and other equipment APB: Mainly used to control the serial port, AD,I2C and other devices above the bus clock divider factor in the RCC_CFGR register 10 to 15 bit settings

2. Clock output

• A total of two microcontroller clock output feet
  
  1. MCO1: Configure the Prescaler to select four clock source outputs to the MCO1 pin
     (PA8) HSI LSE HSE PLL
     Configure mco1pre[2:0] and mco1[1:0] bits to select the given clock source above
  2. MCO2: Configure the Prescaler to select four clock source outputs to the MCO2 pin (PC9)
     HSE PLL SYSCLK plli2s
     Configure mco2pre[2:0] and MCO2 bits to select the clock source given above

Another: The maximum frequency of the output clock must not exceed 100MHz, because the pin at the highest speed of not more than 100MHz

3. Clock measurement

STM32F407ZG allows the capture of clock sources with TIM5 Channel 4 and TIM11 Channel 1, which indirectly measures the frequency of all on-chip clock sources

• TIM5 Channel 4

  The TIM5 has a multiplexed controller that can be used to select whether the input capture is triggered by I/O or by an internal clock. The Tim5_or can be selected by setting the TI4_RMP [1:0] bit.
  To measure LSI clock frequency setup steps:

  1. Enable TIM5 clock and configure Channel 4 for input capture mode
  2. Set the TI4_RMP bit of the Tim5_or register to 0x01 to connect the LSI clock
  3. Capture/Compare measurement of internal clocks with TIM5 4 events or interrupts
     4. Programming the watchdog clock output with the measured LSI frequency to update the RTC Prescaler

• TIM11 Channel 1

  The TIM11 has a multiplexed controller that can be used to select whether the input capture is triggered by I/O or by an internal clock. The Tim11_or can be selected by setting the TI1_RMP [1:0] bit.
  Setup steps are similar to TIM5 Channel 4

4, the value of the PLL setting

F (vco clock) = f (PLL clock input) x (PLLN/PLLM) f (PLL general clock output) = f (vco clock)/PLLPF (USB OTG FS, SDIO, RNG Clock output) = f (VCO clock)/PLLQ

Marking	meaning
F (PLL clock input)	That is, the clock input to the PLL phase-locked loop, the input source can be selected, the system just power up is the HSI source, see below: System Reset clock settings
F (VCO clock)	For the time being to be output after the octave frequency, after the frequency divider set, the size of the chip hardware-related
F (PLL general clock output)	The clock frequency of the actual output of the PLL, referring to the middle part of the STM32 clock tree sysclk 168MHz max, the clock frequency of this point is f (PLL general clock Output), which is then divided for use by different devices
F (USB OTG FS, SDIO, RNG clock output)	That is, the frequency of USB sdio and so on, usually 48MHz

5. Clock Tree Chart

Compare s3c2440 with the STM32, which is cortex M4 's clock graph (the s3c2440 picture is clearer and more detailed.)

STM32 Clock Tree Chart :

s3c2440 Clock Tree Chart :

ARM's clock is basically the PLL phase-locked loop structure, then separated FCLK,PCLK and HCLK to the system core, on-chip peripherals, as well as hardware to provide clocks. 6. Clock setting when system reset

Register Device	Reset Value	meaning
Rcc_cr	0x00000083	Turn on HSI, the system is running just on the power is the HSI for the clock source operation
Rcc_pllcfgr	0x24003010	PLLQ = 4, HSI is the source of the PLL, PLLP = 2,PLLM = 16,plln = 192
Rcc_cfgr	0x00000000	System clock is not divided, the system clock source is HSI

STM32F407ZG Register address mapping :

7. The simplest programming example of clock initialization

#defineBym_rcc_struct\((rcc_typedef*) (Ahb1periph_base+ 0x3800))#defineBym_flash_struct\((flash_typedef*) (Ahb1periph_base+ 0x3c00))#definef_vco_clk_336 ((336 << 6)|(8 << 0))#definepll_out_clk_168 (0 <<  -)#defineUSB_OUT_CLK_48 (7 <<  -)/ * * Initialize system clock * f (VCO clock) = f (PLL clock input) * (PLLN/PLLM) * F (PLL general clock output) = f (VC O clock)/PLLP * F (USB OTG FS, SDIO, RNG clock output) = f (VCO clock)/pllq * * PLLP = 2; PLLQ = 7; PLLN/PLLM = 42; * F (PLL clock input) = 8M;  F (VCO clock) = 336M; * F (PLL general clock output) = 168M; F (USB OTG FS, SDIO, RNG clock output) = 48M */voidSys_clk_init (void){/ * Open HSE high-speed external clock * /Bym_rcc_struct -CR&=~(1 <<  -);//disable HSE, be required by bit18 if you want to write bit18Bym_rcc_struct -CR&=~(1 <<  -);//hse not bypassedBym_rcc_struct -CR|=(1 <<  -);//enable HSE     while((bym_rcc_struct -CR&(1 <<  -))== 0);//wait for HSE ready    /* Set the multiplier factor to determine the clock frequency (PLL mode) */Bym_rcc_struct -Pllcfgr&=~(0xf <<  -);//clear old DataBym_rcc_struct -Pllcfgr|=usb_out_clk_48;//flush New DataBym_rcc_struct -Pllcfgr&=~(0x3 <<  -);//clear old DataBym_rcc_struct -Pllcfgr|=pll_out_clk_168;//flush New DataBym_rcc_struct -Pllcfgr&=~(0x7fff << 0);//clear old DataBym_rcc_struct -Pllcfgr|=f_vco_clk_336;//flush New Data    / * Select the PLL source as HSE, turn on the PLL * /Bym_rcc_struct -Pllcfgr|=(1 <<  A);//hse oscillator Clock selected as PLL and plli2s clock entryBym_rcc_struct -CR&=~(1 <<  -);//close plli2sBym_rcc_struct -CR|=(1 <<  -);//enable PLL     while((bym_rcc_struct -CR&(1 <<  -))== 0);/* Enable instruction prefetch with instruction data cache (the debug process finds this step is necessary, otherwise the program cannot run) */Bym_flash_struct -Acr|=(1 << 8);//Bym_flash_struct -Acr|=(1 << 9);//enable ICacheBym_flash_struct -Acr|=(1 << Ten);//enable DcacheBym_flash_struct -Acr|=(5 << 0);//wait    / * Configure the Prescaler to divide the clock * /Bym_rcc_struct -CFGR&=~(0x7 <<  -); Bym_rcc_struct -CFGR|=(4 <<  -);//APB2 Max value = 84M, 2 devided as System clock = 168MBym_rcc_struct -CFGR&=~(0x7 << Ten); Bym_rcc_struct -CFGR|=(5 << Ten);//APB1 Max value = 42M, 4 devided as System clock = 168MBym_rcc_struct -CFGR&=~(0xf << 4);//system Clock not devided    / * Select the system clock Source * /Bym_rcc_struct -CFGR&=~(0x3 << 0); Bym_rcc_struct -CFGR|=(2 << 0);//PLL used as system clock     while((bym_rcc_struct -CFGR&(2 << 2))== 0); Bym_rcc_struct -CR&=~(1 << 0);//close HSI     while((bym_rcc_struct -CR&(1 << 1)));}

8. Steps to initialize the clock, PLL mode

• Open HSE high-speed external clock
• Set the multiplier factor to determine the clock frequency (PLL mode)
• Configure the Prescaler to divide the clock
• Select the PLL source as HSE, turn on the PLL
• Enable command prefetching with instruction data cache (the debug process finds this step is necessary, otherwise the program cannot run )
• Select the system clock source

Some of the steps can be disrupted by the above procedure, but you must select a PLL source and set the multiplier factor before turning on the PLL. Icache and Dcache must be started before thesystem clock source can be set. To close the HSI, the above steps will not be able to shut down, because the system after the default is HSI is the system clock source and use the PLL, so when the HSI is still in use is not possible to be closed, only the system clock source changes can be closed , Turn off HSI to conserve power

STM32 's Clock