STM32 Architecture Related

Sort out the underlying structure associated with STM32 to help digest understanding

First several pictures (the main reference stm3210x series)

1. Chip structure Composition diagram:

2.STM32 Internal structure:

3.CORTEX-M3 Module Structure diagram:

4.STM3210X Internal structure:

Bridge:

four active units:M3 Core Icode Bus (i-bus), Dcode Bus (d-bus), System bus (S-bus), DMA (DMA1, DMA2, Ethernet DMA) Four passive units: internal SRAM, internal Flash, FSMC, AHB to APB Bridge Icode bus:         Connect the M3 kernel's instruction bus to the flash instruction interface for instruction Prefetching   Dcode bus:Connecting the data bus of the M3 core to the Flash data interface, constant loading and commissioning system bus:Connect the M3 kernel's system bus to the bus matrix to coordinate the kernel and DMA access   DMA bus:         Connect the DMA AHB Master interface to the bus matrix to coordinate CPU Dcode and DMA access to SRAM, Flash, and peripherals Bus matrix:         Coordinates the access arbitration between the kernel system bus and the DMA Master bus, and the arbitration uses a rotation algorithm that includes Dcode, System bus, DMA1 and DMA2 bus, passive unit AHB to APB Bridge:         Two AHB/APB bridges provide synchronous connections between AHB and two APB buses APB1 Speed Limited to 36MHZ,APB2 full speed up to 72MHz

One, clock structure ( clock and reset module, as shown in the upper part of the reference )

After the system is reset, all peripherals are turned off, except for the SRAM and Flash Interface (FLITF).the peripheral clock needs to be turned on before using the peripheralSets the RCC--AHBENR register. Second, the storage structure: ( refer to the upper part ) * Storage Organization:         The CORTEX-M3 storage System uses the unified address method, the small end way 4GB in the linear addressing space, the address space is divided into 8 main block Block0-block7, each block 512MB. On-chip Flash: Starting with 0x00000000 (absolutely speaking from 0x08000000 start, to 0x0800x xxxx end, the program will burn into the inside. ) on-chip SRAM: Starting from 0x20000000 (The random memory used to save temporary data generated by the program runtime, the run-time variable, where the stack is storedIncludes: Code spatial data space segment, bit segment alias register on-Chip peripherals External memory External Peripheral expansion extension: E2prom, storing the data that needs to be saved; FSMC bus can also extend nor and NAND; *flash:The main block consists of the main block and the information block:

Store User program, up to 512KB address range: 0x0800 0000–0x0807 FFFF Small capacity: 16k-32k, Max 4kx64bit, Total 32x1k page capacity: 64k-128k, Max 16kx64bit, Total 128x1k page bulk: 256k-512k, Max 64kx64bit, total 256x2k page small capacity: 16k-32 K, Max 4kx64bit, total 32x1k page interconnect type: Max 32kx64bit, total 128x2k page

Information Block:

System Memory 2kb:0x1fff f000–0x1fff f7ff ISP bootloader program Option Bytes 16b:0x1fff F8 00–0X1FFF f80f

*sram:Maximum 64KB address range: 0x2000 0000–0x2000 FFFF * on-chip Peripheral address mapping: * bit segment (Bit-band), bit segment alias:The M3 storage space includes two bit segments, which can be manipulated in a word, and can be manipulated in the minimum 1MB space of SRAM: 0x2000 0000–0x200f FFFF Peripheral Minimum 1MB space: 0x4000 0000–0x400f FFFF A. To facilitate the operation of the segment area, a two 32M bit segment alias Area B. A word C in the alias area of each bit segment in the bit segment area. By reading and writing a word in the alias area, you can implement a read-write operation alias area for a bit in the bit area, 2 32mb:sra m:0x2200 0000–0x21ff FFFF        Peripherals: 0x4200 0000–0x41ff The bit mapping formula for the word and bit segment area in the FFFF bit segment alias area: bit_word_addr = bit_band_base + (Byte_offset x +) + Bit_number x 4 For example: In the SRAM Segment area address 0x20000300 byte median 2 0x22006008 = 0x22000000 + (0x300 x +) + (2 x 4) write to a word in the alias area: the No. 0 bit of the word will The corresponding bit in the affected bit area reads a word in the alias area: if the corresponding bit in the bit area is 0, the result is 0x0, and if the corresponding bit in the bit area is 1, the result is 0x1 PS:The read and write of the alias area can realize the atomic operation of each bit in the bit area, and only need one instruction to realize  * Startup mode: STM32 system Boot area: 0x0000 0000–0x0007 ffff,512kb system starts: The CPU starts executing code from 0x0000 at ScanDisk 0000 address      the area is actually neither flash nor SRAM, and after the boot configuration, the actual boot zone is mapped to the ScanDiskAfter the system resets, on the 4th rising edge of the SYSCLK, the boot pin state is saved and the user selects the boot mode by setting the BOOT1,BOOT0 pin state the CPU executes code from ScanDisk at 0x0000 0000 address 0x0000 0000 actually SP 0x0000 0004 is the address of the executing code, even if it is mapped to ScanDisk, the boot pin status can still be re-saved after the original storage space access related memory is exited from standby mode. When standby, the boot pin must be kept stm32f10x by configuring the boot[1:0] pin to select three different boot modesthird, on-chip peripherals stm32f10x Peripherals

STM32F103XX enhanced large-capacity peripherals

Four, GPIO structure

Shared? (5) x 16 I/O ports:

• PA0 ~ PA15
• PB0 ~ PB15
• PC0 ~ PC15
• PD0 ~ PD15
• PE0 ~ PE15

3.3V compatible with 5V:

• PA8 ~ PA15
• PB2 ~ PB4, PB6 ~pb15
• PC6 ~ PC12
• PD0 ~ PD15
• PE0 ~ PE15

Only 3.3V Supported:

• PA0 ~ PA7, and do adc_in0 ~ adc_in7
• PB0 ~ PB1, and do adc_in8 ~ adc_in9
• PB5
• PC0 ~ PC5, and do adc_in10 ~ adc_in15
• PC13 ~ PC15

Pin (48 64 ... ) Development Tools

Advantages of the STM32 series

Advanced core architecture, the STM32 series uses Arm's latest, advanced architecture cortex-m3 Core Power control, STM32 processor with three low power modesoperating mode uses an efficient dynamic power consumption mechanism, when running at 72MHz full speed in flash, if the external clock is turned on, the processor consumes only 27mAvery low power consumption at standby, Typ. 2uAprovides low voltage 2.0~3.6v working capability when battery is poweredFlexible clock control allows users to optimize for their desired power consumption/performance requirements RTC can be independently powered, external button battery

on-chip peripherals with outstanding performance and innovative features        STM32  processor-on-chip peripherals benefit from dual  APB  bus architecture          There is a high speed  APB with a speed of up to cpu  and the peripherals connected to the bus can run at a higher speed                  usb:   12mbit/s                         usart:  4.5mbit/s                 PI:&N bsp;  18mbit/s                       IIC: &NBS p;  400khz                 Gpio:  18mhz Flip                       pwm:     timer 72MHz input           Some functional innovations on on-chip peripherals for the most common motor control,stm32  in  MCU  applications             & nbsp     Built-in timers and adc  for three-phase brushless motor control                Advanced PWM timers available:                         6 PWM output    -> die-out      ->  edge alignment and center-to-'s what-shape                          Encoder input      ->&nbs p; Hall sensor    ->  complete vector control ring emergency stop,                         can be synchronized with 2-way ADC, synchronized with other timers programmable guard mechanism can be used to prevent illegal write to registers                &NBSP Dual ADC Sample/Hold, 12-bit 1uS, continuous/standalone mode, multi-trigger source                  etc.

STM32 Architecture Related