Stm32 Firmware Library: interrupted __ interrupted

1. Introduction:

The STM32 can support 68 external interrupt channels, which have been fixed to the corresponding external devices. Each interrupt channel has its own interrupt priority control byte Pri_n (8-bit, but only 4-bit in the STM32, high 4-bit valid) there can be 5 groups in total:

Group No. 0: All 4 bits are used to respond to interrupts

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Group 1th: Maximum 1 bits for preemption priority, lower 3 bits for response interrupts

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Group 2nd: Maximum 1 bits for preemption priority, lower 3 bits for response interrupts

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Group 3rd: Maximum 1 bits for preemption priority, lower 3 bits for response interrupts

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Group 4th mode: all 4 bits for response interrupts

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

2. Settings in the firmware library:

    Nvic_prioritygroupconfig (nvic_prioritygroup_2);	      Interrupt Grouping 2
    nvic_initstructure.nvic_irqchannel = usart1_irqn; 	      USART1 receive interrupt
    nvic_initstructure.nvic_irqchannelpreemptionpriority = 0;//First priority 0
    Nvic_initstructure.nvic_ irqchannelsubpriority = 0;	      Secondary account priority
    Nvic_initstructure.nvic_irqchannelcmd = ENABLE;
    Nvic_init (&nvic_initstructure);

"1" for the entire program, you need to set up an interrupt grouping, set the function as follows:

void Nvic_prioritygroupconfig (uint32_t nvic_prioritygroup)

The parameters are evaluated as follows:

Nvic_prioritygroup_0

Nvic_prioritygroup_1

Nvic_prioritygroup_2

Nvic_prioritygroup_3

Nvic_prioritygroup_4

"2" and then instantiate a NVIC structure body:

typedef struct
{
  uint8_t nvic_irqchannel;                    /* Specifies the IRQ Channel * *
  uint8_t nvic_irqchannelpreemptionpriority;  /* First Priority * *
  uint8_t nvic_irqchannelsubpriority;         /* Secondary Account Priority * *
  functionalstate nvic_irqchannelcmd;         /* control command   
/} nvic_inittypedef;

A. Interrupts with a high preemptive priority (small number) interrupt a lower preemptive priority interrupt service and constitute an interrupt nesting.

B. When 2 (n) interrupts occur with the same preemptive priority, they cannot constitute an interrupt nesting, but STM32 first responds to a high priority interrupt.

C. When a 2 (n) interrupt occurs with the same preemptive priority and the same child priority, the STM32 first responds to the interrupt with a lower interrupt vector address for the interrupt channel.

D. No. 0 Preemptive priority interruption, can interrupt any interrupt preemptive priority is not No. 0 of the interruption, 1th preemptive priority interrupt, you can interrupt any interrupt preemptive priority of 2, 3, 4th interruption;. ; form a nested

E. If two interrupts have the same preemptive priority, who first appears, first responds to WHO, does not constitute a nesting. If you appear together (or hang out there), look at the 2 of them who have higher precedence, and if the child precedence is the same, look at their interrupt vector position. Lower address, higher interrupt priority

"3" initializes the NVIC peripherals according to the NVIC structure:

void Nvic_init (nvic_inittypedef* nvic_initstruct)