STM32F4_RCC system clock Configuration and description

Ⅰ , overview

For the system clock should know its role, is to drive the whole work of the heart of the chip, if not, it is equal to the person has no heartbeat.

For friends using board learning, the knowledge of the RCC system clock is not well configured, because the crystal oscillator provided by the board is basically the official standard clock frequency, using the official standard library, so that the system clock is the default configuration, also is the default frequency. However, configuring the system clock is necessary for a friend to design a development board, or to change the system clock frequency (e.g., to reduce power consumption).

About clocks this piece of peripherals related to timers (TIM, RTC, WDG, etc.) is also important, because precision is required and the clock frequency is accurate.

This article will describe the system clock configuration and attention to the relevant matters, more details, please look down.

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Ⅱ, about clocks

1. Clock classification

The clocks of the STM32 chip (all models) contain 4 classes:

HSE (High speed External) fast external clock

HSI High speed Internal Internal clock

LSE (Low speed External) slow external clock

LSI (Low speed Internal) slow internal clock

2. Clock source

STM32 chip (all models) the clock source that drives the system clock:

HSI Internal high-speed clock

HSE External high-speed clock

pllclk Frequency multiplier clock

The STM32 has the following two secondary clock sources:

Up to kHz Low speed internal RC (LSI RC), the RC is used to drive independent watchdog and optionally available to RTC for automatic wake-up in shutdown/Standby mode.

32.768 kHz Low Speed external crystal (LSE oscillator) for driving the RTC clock (RTCCLK). For each clock source, it can be turned on or off independently when not in use to reduce power consumption.

3. Clock tree (block diagram)

There may be differences between the clock trees on STM32 for different series of chips. F0, F1 and F3 series chips (the mainstream chip, the frequency is relatively low) there are many similarities, F2 and F4 (high-performance chip) series of chips have many similar places. However, there is a big difference between the clock trees of the F3 chip and the F4 chip, as detailed in the reference manual, RCC-related chapters.

The STM32 clock Controller provides a high degree of flexibility for applications where the user can choose to use an external crystal when running the core and peripherals or use an oscillator, either at the highest frequency or at the right frequency for Ethernet, USB OTG FS, and other peripherals requiring a specific clock, such as HS, I2S, and Sdio.

Take the F417 chip as an example: the AHB frequency, high speed APB (APB2), and Low Speed APB (APB1) can be configured with multiple prescaler. The maximum frequency for the AHB domain is 168 MHz. The maximum allowable frequency for high-speed APB2 domains is. The maximum allowable frequency for a low-speed APB1 domain is at-MHz. The actual output of the maximum clock can be improved a bit, but in order to ensure that in a variety of environments, it is best not to exceed the standard maximum value.

The stm32f4xx device has two plls:

The primary PLL (PLL) provides a clock signal from a HSE or HSI oscillator and has two different output clocks:

The first output is used to generate a high-speed system clock (up to 168 MHz)

The second output is used to generate a USB OTG FS clock (x MHz), and a random number generator clock

The dedicated PLL (plli2s) is used to generate accurate clocks to Achieve high-quality audio performance on the I2s interface.

Due to PLL enable the Emperor PLL configuration parameters cannot be changed, so it is recommended to first PLL Configure, then enable (select hsi or hse oscillator as PLL clock source, and configure the crossover factor m , n , p and q

The Plli2s uses the same input clock as the PLL ( pllm[5:0] and pllsrc bits of two PLLs shared). However, the plli2s has special enable / Disable and crossover coefficients ( N and R ) configuration bits. after the plli2s is enabled, the configuration parameters cannot be changed.

Ⅲ, Code Analysis

Take the stm32f4x5, X7 series of chips as an example to analyze the configuration of the system clock.

Reference Software Engineering:

https://yunpan.cn/cRepWDShSK4yc access password 65b1

1. Frequency multiplier parameter

combined with the above clock tree and source code can be seen, the system clock PLLCLK The main calculation is the configuration Pll_m , Pll_n , pll_p these three parameters, and finally 168M is through the frequency division, octave out.

2. Verify the clock frequency

For the STM32 chip, verify that the system clock eventually runs at a speed that the most accurate verification method uses an oscilloscope to test its system clock.

Here is a description of how to test the system clock with an oscilloscope. In fact, it is very simple to configure the clock output in the software code (here can output many types of clock HSE, HSI, PLLCLK, etc.), according to the code configuration, the corresponding output clock is different. Please look at the source code:

I have this option in the code I provide, and this feature is turnedon by configuring the definition to 1. The parameters of the clock output are two, the clock source, the crossover value. Note: The maximum output clock here is 100M, so the pllclk Clock is divided before it can be output, otherwise you will not be able to detect the waveform with the oscilloscope (I tested it).

The last output waveform

Ⅳ , Description

About the development of STM32, software compatibility is very good, do not feel that your chip and I summed up the example of the difference does not look, in fact, is the wrong understanding, especially the same series of chips basically the program is compatible, that is, can use each other.

The above summary is for reference only, if has the wrong place, please understanding.

Ⅴ, last

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STM32F4_RCC system clock Configuration and description