STM8S--PWM Configuration

The chip used in this article is ipv8s103f3.

The following describes how to configure tim2 Channel 1 as the PWM output.

1. Register Configuration

4-bit pre-divider, counter counting frequency fck_cnt = fck_psc/2 ^ (PSC []) = 16 m/2 ^ 0 = 16 m

The count cycle is 1/16 us, that is, the counter counts every 1/16 us.

Tim2_pscr = 0x00; // frequency division = 0 16 m

Automatic Reload register,

When the automatic reload register is set to 0, the counter is in the blocking status, that is, not counting status, because when the cntr is set to ARR, The cntr is cleared, therefore, the automatic reload register should be greater than 0 during configuration. In addition, the value of the Automatic Reload register is the period of the PWM waveform. For example, if arr = 0x0100, the period of the PWM is 0x0100*1/16 = 16us, and the period of the PWM is 16us.

Tim2_arrh = 0x01; // The value of automatic reinstallation is 0x0100.

Tim2_arrl = 0x00;

Capture/compare enable registers. The configuration of this register can be selected through the corresponding tim2 channel.

Bit5, bit4 for CH2 configuration, bit1, bit0 for Shard Configuration

If oc1 is the output channel

Bit1: oc1 low-level valid

Bit0: The oc1 signal is output to the current pin.

Tim2_ccer1 = bit0 | bit1; // low level, oc1

Capture/compare mode register,

Bit1, bit0

Select capture/comparison for cc1s [1:0]

00: the PC3 channel is configured as output

Bit2 Reserved

Bit3 outputs compare pre-loaded enable

0: No

1: Enable

Bit6, bit5, and bit4 output comparison Modes

110: pwm1 Mode

Differences between pwm1 and pwm2 Modes

Pwm1: CNT <CCR, activation

Pwm2: CNT> Cr, activation

Tim2_ccmr1 = bit3 | bit5 | bit6; // Mode

Capture/compare registers, which determine the duty cycle of PWM. Cr/ARR = PWM duty cycle. For example, if it is set to 0x0060, the duty cycle is 0x0060/0x0100 = 6/16.

Tim2_ccr1h = 0x00;

Tim2_ccr1l = 0x60;

Interrupt enable register, which can be set here if you need to interrupt.

Bit1: cc1e capture/compare 1 interrupt enable

0: the service is interrupted.

1: Service Interruption

Tim2_ier = 0x00; // update interrupt enabling

Control Register. bit0 controls the opening and closing of counters.

Bit0, counter enabling

0: No

1: Enable

Tim2_cr1 = bit0; // enable counter

Test the output level of the pd4 pin through the logical analyzer, as shown in the following figure.

The source code is as follows,

//************************************** *****

1 # define bit0 0x01 2 # define bit1 0x02 3 # define bit2 0x04 4 # define bit3 0x08 5 # define bit4 0x10 6 # define bit5 0x20 7 # define bit6 0x40 8 # define bit7 0x80 9 10 void timer2_init (void) 11 {12 clk_ickr | = 0x01; // enable the internal HSI 13 while (! (Clk_ickr & 0x02); // HSI is ready. 14 clk_swr = 0xe1; // HSI is the main clock source. 15 clk_ckdivr = 0x00; // Hsi, 8 frequency = 16 M 16 tim2_pscr = 0x00; // frequency = 0 16 M 17 tim2_arrh = 0x01; // auto-Reload value 0x0100 18 tim2_arrl = 0x00; 19 tim2_ccer1 = bit0 | bit1; // low level, oc120 21 tim2_ccmr1 = bit3 | bit5 | bit6; // mode 22 tim2_ccr1h = 0x00; 23 tim2_ccr1l = 0x60; 24 tim2_ier = 0x00; // update interrupt enabling 25 26 tim2_cr1 = bit0; // enable counter 27} 28 int main (void) 29 {30 timer2_init (); 31 While (1) {}; 32}