Strong Arm sa1110 USB Solution

Strong Arm sa1110 USB Solution

USB interface solution for strong arm sa1110

■ Li mengshu yunxing, computer department, Luoyang Industrial College

Because intel strong arm sa1110 has a clock speed of up to MHz and has powerful multimedia interfaces and LCD interfaces, it has been widely used in handheld computers and some industry users, such as China Telecom's multimedia public calls and VoIP mobile terminals. However, because the sa1110 USB interface only has a Slave controller and can only be used as a slave device, which limits the application scope of sa1110, how to extend the USB main interface for sa1110 becomes a key issue. Two USB primary interfaces and one slave interface are extended for sa1110 using isp1161 of Philips. Isp1161 features Isp1161 integrates two USB controllers on one chip, one is the master controller HC (host controller) and the other is the Slave controller DC (device controller). The two controllers share bus interfaces, with independent DMA channels and independent DMA interrupt request pins, independent master interface and slave interface, isp1161 can control the simultaneous operation of usb hc and DC. Isp1161 provides two downstream ports for usb hc and one upstream port for usb dc. Each downstream port has an independent overcurrent detection input pin and a power supply switch control output pin. The upstream interface has an independent vbus detection input pin. Therefore, Two USB master interfaces and one slave interface can be extended for the sa1110. The USB main interface can be connected to any USB device compatible with the USB interface protocol, and the USB slave interface can be connected to any USB main interface compatible with the USB interface protocol. At the same time, usb hc and DC have independent wake-up input pins and hanging output pins, making the system power management more flexible. Therefore, isp1161 is ideal for embedded systems and portable devices. Application 1 in an embedded system that uses isp1161 is shown in. Isp1161 performance indicators Isp1161 supports the USB2.0 Protocol and is compatible with USB1.1; Supports single-channel burst mode and multi-channel burst mode DMA operations; Built-in independent buffer HC (4 kb) and DC (2462bit ); Operating Voltage + 5 V or 3.3 V; 8 kV ESD circuit protection; The maximum transmission speed of the primary interface is 15 Mb/s, and the maximum transmission speed of the secondary interface is 11.1 Mb/s; 6 MHz Crystal Oscillator with built-in PLL to reduce electromagnetic interference (EMI ). Connection Method The interface between isp1161 and CPU. It is designed specifically for the CPU of the CPU. Data Transmission can work in the I/O port mode and DMA mode. Internally, there is a "ping pong" structure of ram that can be controlled by internal master/Slave controllers or external CPUs. The allocation of this ram space is independent of the master controller and Slave controller. The master controller has 2 k Ping Ram and 2 k Pong Ram, the Slave controller has K Ping Ram and K Pong Ram. The D0-D16 of isp1161 is directly connected to the sa1110 data line and uses the two address lines of sa110 (A0, A1) to select the internal register of isp1161. A1a0 = 00 select the data port of the master controller; A1a0 = 01 select the command port of the master controller; A1a0 = 10 select the data port of the Slave controller; A1a0 = 11 select the command port of the Slave controller. A SC of sa1110 is used to allocate a fixed address for isb1161. WR and RD send write and read Signals respectively. Int1 and int2 are Master/Slave interrupt applications connected to the sa1110 gpio, which are programmable for level or pulse triggering. The isp1161 reset/N is connected to the reset_out/N of sa1110, And the reset_out/n automatically generates a low level after the sa1110 reset to reset isp1161. Connection 2 is shown in. Read/write Sequence Modify the memory read/write cycle of sa1110 by setting the msc0, MSC1, and msc2 registers. Writing msc0 can change the read/write cycle of CS0 and CS1, writing MSC1 can change the read/write cycle of CS2 and CS3, and writing msc2 can change the read/write cycle of CS3 and cs4. Read operations must follow the following sequence relationships: According to the read/write cycle of isp1161, The mscx register that controls the isp1161 chip line selection can be set accordingly, so that the read/write sequence of isp1161 in sa1110 can meet the requirements of isp1161 chip. There are two steps to access the internal register of isp1161: 1) write the Register address to be accessed; 2) data transmission according to (RD/WD) requirements. Interrupted use Two interrupt int1 and int2 of isp1161 are generated by the master controller and Slave controller respectively. interrupt control is implemented by setting the interrupt register, interrupt enable register and hardware configuration register of isp1161. Int1 and int2 can be set to four working modes: high level, low level, rising edge, and falling edge. Connect the gpio ports int1 and int2 to sa1110 respectively. Each gpio port can set the corresponding bit in the rising edge detection register (grer) and the falling edge detection register (GFER, detects int1 and int2 changes along the edges and generates CPU interruption notifications. Isp1161 suspension and Restoration Isp1161 is designed for embedded devices and provides energy-saving working modes to reduce power consumption. isp1161 can be switched to energy-saving mode by setting control registers of the master controller and mode registers of the Slave controller. Master controller suspension settings, write 11 to the control registers of bit7, 6 master controller function status bit (hcfs), you can achieve the master controller suspension, into the pending state of 1, 3 ms, internal clock stopped, the internal voltage regulating circuit is closed, and the read pin h_suspend level can determine whether to suspend the operation. From the Controller suspension settings, send a high-level pulse to the bit 5 (gosusp) of the mode register, the Slave controller can be suspended, read pin d_suspend level, you can determine whether to implement the suspension operation. The wake-up function of isp1161 is implemented by controlling the h_wakeup and d_wakeup pins of the master controller, which can be connected to the sa1110 gpio. You can also set the isp1161 control register's bit3 to 1 and wake up through the CS signal, that is, when the CS signal is effective, the system can be awakened.