Sub-steady state problems in Asynchronous Reset design and Their Solutions

1 Introduction

 

Resetting is a basic and important issue in ASIC design. Designers can choose synchronous or Asynchronous Reset. Synchronous Reset combines the trigger of light music to save the number of design doors. For the simulator of the basic cycle, it is much easier to perform synchronization reset [3]; In Synchronous Reset, the clock plays a role in filtering reset signal glitch. However, Synchronous Reset requires a pulse width extender to ensure that the reset signal has a certain pulse width to ensure that the effective edge of the clock can be sampled to [6]; the designer must use a pessimistic simulator to compare the optimistic one. During the simulation process, the reset signal may be overwritten by the X-State. If the ASIC or FPGA contains an internal three-state bus, to prevent competition of the internal three-state bus when the chip is powered on, the chip for Synchronous Reset must have an on-Power Asynchronous Reset [2]. These are the advantages of Asynchronous Reset. The biggest advantage of Asynchronous Reset is that the data path can be clean and controllable without relying on the clock.

 

However, asynchronous resetting also has inherent defects. The DFT (testability design) and sta (static timing analysis) of Asynchronous Reset design are more complex than Synchronous Reset design. However, the most serious problem in Asynchronous Reset is that, if the Asynchronous Reset signal is "released" when the trigger clock is effective (the reset signal changes from effective to invalid), it may cause the sub-steady state output by the trigger [1]. This article analyzes the causes and consequences of this problem and provides a possible solution.

 

2. Asynchronous Reset

 

Many designers use Asynchronous Reset because they like this idea to put their circuits completely in a controllable state by resetting. However, many designers only use Asynchronous Reset to ignore possible problems. They perform a reset test in a controllable simulation environment, and everything works normally. However, real systems encounter intermittent errors. Designers often underestimate the "release" issue of Reset signals in real systems (uncontrollable environments. This problem may cause the chip to enter an unknown sub-steady state, thus making all the reset ineffective.

 

2.1 substable generation and impact

 

As shown in 1, trecovery (recovery time) refers to the release of the original valid Asynchronous Reset signal (for low-level effective reset, It is the top hop edge) the minimum time required between the time and the first effective clock edge that follows the clock. Tremoval (removal time) refers to the minimum time required between the effective clock edge and the original valid Asynchronous Reset signal after it becomes invalid. If the upstream hop of the Asynchronous Reset signal (taking the low level as an example) falls within the trecovery and tremoval windows, the output value of the trigger is uncertain and may be high, it may be a low level, may be between high and low levels, or may be in a shock state), and will be fixed to a high or low level at an unknown moment. This state is called the sub-steady state. Reflected in the simulation model, the output value is an indefinite X. In the figure, tclk-Q is the latency from the trigger's clock end to the Q end, and tmet is the maximum time allowed to ensure that the sub-steady state does not spread to the next level.

 

The above problem does not exist in the Synchronous Reset circuit. In an asynchronous circuit, because there is no time relationship between the external reset signal and the internal clock, the recovery/removal conflict is inevitable and the sub-Steady State will inevitably occur. When a signal is locked by a register, if the setup/hold time is not met between the data signal and the clock, the output end will also have a sub-steady state, which is not in the scope of this article [4].

 

The effect of the sub-steady state on the Logical Functions of the circuit is obvious. The sub-Steady State also has physical influences on the circuit. In the CMOS process, the transistor is in the conduction state only when the output is flipped. There is a large conduction current, and the input is stable at a high or low level, the transistor does not turn on. At this time, there is only a small leakage stream. Because the sub-steady state level may be between high and low levels, it will make the next level of transistor in the conduction state, consuming a lot of energy.

 

2.2 assessment of sub-steady state

 

Mean Time (MTBF) (mean time between failures)

 

The MTBF of a single trigger is given by the following formula:

 

 

In formula, tmet is the maximum time allowed to ensure that the sub-steady state does not spread to the next level; C1 and C2 are constants related to the trigger nature; fclock is the clock frequency; freset is the conversion frequency of the Asynchronous Reset signal. It can be seen that MTBF is very sensitive to changes in tmet. In typical cases, MTBF is measured in 4 years.

 

Formula (1) the estimation result is only for a single trigger. What will happen if the Asynchronous Reset design shown in 2 is used without any measures to prevent the sub-steady state?

Assume that there are n Asynchronous Reset triggers in the entire ASIC, And the reset signal of each trigger is asynchronous with the clock signal, then the MTBF of each trigger is obtained by formula (1, then the average no-fault time of the entire chip mtbfc will be: kvaunb |-J 4en = + ^ & = \ hvog84nq/W \ @ hfpnq2,; "uh

 

 

With the current chip integration, a design may include millions of triggers, namely N-106, MTBF. In seconds. It can be seen that the async reset shown in step 2 will have a great impact on the sub-stable state without taking any measures.

 

3. Problem Solving

 

As mentioned above, the sub-steady state in the synchronous circuit can be completely avoided. The sub-steady state in the asynchronous circuit cannot be avoided, and the impact can only be reduced to a tolerable range. To solve this problem, use the reset Synchronization Circuit shown in 3. As shown in 3, the data input of the first-level master reset trigger is bound to a high level. As the Asynchronous Reset signal is revoked, the input clock sampling is allowed, the output end is then output to the second-level master reset trigger and then synchronized through the first-level clock to obtain a master reset signal masterrst_n. The master reset signal then reaches each destination register and trigger in the design through the reset allocation buffer tree.

 

Why can the Synchronization Circuit shown in Figure 3 solve the problem of Asynchronous Reset? This is due to the following two points: ① The use of the reset synchronizator converts the Asynchronous Reset signal to the reset signal synchronized with the clock, at the same time, the two-level trigger can be used to form a reset synchronizer, which may greatly reduce the sub-steady state of the synchronization; ② The use of the reset allocation buffer tree corrected the propagation delay difference between the main reset signal and the trigger for each target, ensuring the consistent transmission of the reset signal;

 

3.1 reset Synchronization

 

The function of the reset synchronizator is to generate a stable reset signal synchronized with the clock. It is not difficult to obtain a signal synchronized with the clock. The key lies in how to ensure the signal stability, that is, to ensure that the effect of the sub-steady state is reduced to a tolerable level. This is the reason why two-level triggers are used to form a synchronization device. The following describes the sub-steady state of the two-level triggers for evaluation.

 

The average fault-free time of the first-level trigger is recorded as MTBF (1). It has been obtained from formula (1). For the two-level trigger, the specific method is to use the two-level trigger design shown in 3. MTBF (2:

 

 

Therefore, the average no-fault time of the second-level register is:

 

 

Obviously, MTBF (2) is much larger than MTBF (1). As mentioned above, MTBF (1) is measured in years. If MTBF (1) is 100a, MTBF (2) it is about 10 000a. In fact, if a product requires mass production, MTBF must be large enough [4]. The reset synchronization system consisting of two-level triggers basically reduced the sub-steady state problem to a tolerable level.

 

3.2 reset allocation buffer tree

 

As shown in figure 3, the signal (Master reset signal masterrst_n) generated by the reset synchronizator is already a signal for clock synchronization. But how can we ensure that it can still synchronize with the clock when it reaches the trigger of various purposes in the chip without generating a sub-steady state? In this case, we need to reset the allocation buffer tree to ensure that.

 

The reset allocation buffer tree (or reset tree) is similar to the clock tree. In addition to increasing the drive capability, it mainly aims to balance the path delay between reset terminal nodes of each trigger. However, the latency difference (Skew) between reset signals is not very strict compared with the clock signal, as long as the delay of the master reset signal is short enough, when the reset signal is transmitted to all load ends within a clock cycle, the recovery time of each target register and trigger is met.

 

The reset tree ensures that all triggers except the primary trigger are correctly reset, so the average time of the entire chip is no fault,

 

 

By contrast (2), we can see that the average no-fault time of the chip is greatly reduced, and the fault rate is reduced to a tolerable level.

 

3.3 instance

 

The Asynchronous Reset policy described above is adopted in a recently designed embedded microprocessor chip, as shown in figure 4. It is worth noting that the clock of the main trigger does not directly introduce the clock at the root of the clock, but uses a later clock. The purpose of this operation is to enable the master reset signal to reach each node in the design as soon as possible, so that it can be easily completed within a clock cycle [1].

 

4 Conclusion

 

Although Asynchronous Reset is an ideal reset circuit method, if improperly handled, the design of Asynchronous Reset will be very serious. An effective way to use the Asynchronous Reset design is to add the reset synchronizator and reset buffer tree to the design. This method combines the advantages of Synchronous Reset design and Asynchronous Reset design. It not only achieves Asynchronous Reset but also reduces the effect of sub-steady state to a tolerable level, thus ensuring the normal design function.

Sub-steady state problems in Asynchronous Reset design and Their Solutions