Synchronous reset and asynchronous reset in FPGA

1. Asynchronous reset

Always @ (Posedge sclk or Negedge s_rst_n)

if (!s_rst_n)

D_out <= 1 ' b0;

else D_out <= A;

The consolidated RTL view is as follows:

You can see that the register d_out has a low-level effective reset signal S_rst_n port, even if the design is high power level, the actual synthesis will also reverse the asynchronous reset signal back to the CLRN end;

2. Synchronous reset

Always @ (Posedge sclk)

if (!s_rst_n)

D_out <= 1 ' b0;

else D_out <= A;

The consolidated RTL view is as follows:

It can be seen that the synchronous reset is not used to register the CLRN port, but the reset signal s_rst_n as the input logic signal, so relative to the asynchronous reset, it increases the logic resource consumption inside the FPGA;

3. Asynchronous Reset vs Synchronous Reset

They have advantages and disadvantages, the internal FPGA register has a dedicated port to support asynchronous reset, the use of asynchronous parts without adding additional logic resources of the device, but the asynchronous reset is also a hidden danger, prone to metastable problems; synchronous reset determines whether the system resets at the rising edge of the clock signal SCLK, This reduces the probability of metastable occurrences (only reduced, impossible to completely avoid);

Synchronous reset and asynchronous reset in FPGA