The--mio of Zynq learning

1, Gpio basic knowledge

　　The ZYNQ7000 series Chip has 54 MIO (MultiUse I/O), which are assigned to the PS portion of the GPIO Bank0 and Bank1, which are directly connected to the PS. There is no need to add pin constraints, and the MIO signal is not visible to the PL portion, that is, PL cannot perform any operation on this part of the IO signal. Therefore, the operation of MIO can be regarded as pure PS operation. Reference chip manuals See

BANK0:MI0[31:0]
BANK1:MI0[52:53]
BANK2:EMI0[31:0]
BANK3:EMI0[63:32]

GPIO 's control register address space

A lot of registers, but the general operation is to focus on some registers on it.

Data_ro:This register enables software to observePINFeet, whenGPIOWhen configured as output, the value of this register will reflect the outputPINFoot condition.
DATA:This register controls the output toGPIOValue that reads the value of this register can be read to the value of the last write to the register.
MASK_DATA_LSW:Bit operation Register, writeGPIOLow16bitOther unchanged positions save the original state
MASK_DATA_MSW:Bit operation Register, write GPIO high 16bit other unchanged position save original state
Dirm: This register controls the output switch, when dirm[x]=0 , suppresses the output
OEN: output Enable, when oen[x]=0 output off, pin foot in tri-state
Therefore, if you want to read the IO state you have to read the value of Data_ro, if you are working on one of them is writing
Mask_data_lsw/mask_data_msw
Please refer to the Technical manual for the specific relevant parameters Ug585-zynq-7000-trm.pdf

2, FPGA hardware creation.

Mio's operating hardware is relatively simple to create, external only need to add Mio external.

Then compile and export the hardware into the SDK software.

3. SDK Software

The first is to create an app project, which is not explained here. Look at the software design, is the pure C development.

　　　　

#include "Xgpiops.h"
#include "Sleep.h"
int main ()
{
Static Xgpiops psgpioinstanceptr;
xgpiops_config* gpioconfigptr;
int ipinnumber= 7;//Board LED connection is MIO7, this according to the board's hardware design to make corresponding changes
U32 upindirection = 0x1;//Sets the IO direction. 1 indicates output, 0 indicates input
int xstatus;

Initialization of the--mio
Gpioconfigptr = Xgpiops_lookupconfig (xpar_ps7_gpio_0_device_id);
if (gpioconfigptr = = NULL)
return xst_failure;

Xstatus = Xgpiops_cfginitialize (&psgpioinstanceptr,gpioconfigptr, gpioconfigptr->baseaddr);
if (xst_success! = xstatus)
Print ("PS GPIO INIT FAILED \n\r");
--mio Input and output operation
Xgpiops_setdirectionpin (&psgpioinstanceptr, ipinnumber,upindirection);//Configure Mio output direction
Xgpiops_setoutputenablepin (&psgpioinstanceptr, ipinnumber,1);//7th bit output of the configuration Mio

Here's how the library function works.
/* while (1)
{
Xgpiops_writepin (&psgpioinstanceptr, Ipinnumber, 1);//Light the 7th bit of Mio output 1
Usleep (500000);//us delay
Xgpiops_writepin (&psgpioinstanceptr, Ipinnumber, 0);//off Mio 7th bit output 0
Usleep (500000);//us delay
}*/

The following is how the register operates.

while (1)

{
Xgpiops_writereg (0xe000a000,0x00000000, 0xff7fffff&0xffff0080);
Usleep (500000);//us delay
Xgpiops_writereg (0xe000a000,0x00000000, 0xff7fffff&0xffff0000);
Usleep (500000);//us delay
}
return 0;
}

Analyze some of the following Xilinx functions:

Gpioconfigptr = Xgpiops_lookupconfig (xpar_ps7_gpio_0_device_id); Find the corresponding ID device exists, if there is no error, if it exists, you can do the next initialization.

can find out

/* Definitions for peripheral ps7_gpio_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xe000a000//This is the base address of Mio.
#define XPAR_PS7_GPIO_0_HIGHADDR 0XE000AFFF//This end address does not need tube

The--mio of Zynq learning