The SDRAM analysis of mini2440

The first is the 2440 storage controller:

For the moment, whether it's starting from NAND or not, because I'm only looking at memory now, from the range that can be seen by the 2440 memory controller is 0x0000,0000---0x4000,0000, which is 1G, and this 1G is divided into 8 bank , BANK0-BANK7, each bank is 128M, 8*128m=1g. Where BANK0-BANK5 these 6 banks can only be connected to Srom, then what is the srom,2440 Data Sheet 221 page description, Srom is ROM or SRAM.

　　

Universal Storage Devices:

How memory storage devices are stored: Rom,ram

ROM(read-only memory): read-only memory, a solid-state semiconductor memory that can read only pre-existing data. The feature is that once the data is stored, it can no longer be changed or deleted. It is usually used in electronic or computer systems that do not require frequent changes to the data and will not disappear due to power off. such as: The BIOS inside the PC.

RAM (Random access memory): Random access memory, the contents of the storage unit can be arbitrarily removed or deposited on demand, and the speed of access to the location of the storage unit independent of the memory. It can be understood that when you give a random, valid access address, RAM returns its stored content (random addressing), and its access speed is independent of the address. This kind of memory loses its storage content during power loss, so it is mainly used to store the program which is used randomly in short time. The memory address in a computer system is a four-byte aligned address (32-bit machine), CPU fetch, execution, storage is through the address, so it can be used to do memory.

RAM According to hardware design, random memory is also divided into dram (dynamic RAM) and SRAM (static RAM) random memory.

DRAM: Its basic original is a small capacitor, the capacitor can be on two plates for a short period of time to retain the charge, can be through the polarity between the voltage difference between 0 and 1 of the computer, due to the physical characteristics of the capacitance, to regularly charge for it, otherwise the data will be lost. The charging process of the capacitor is called refresh, but the production process is simple, small size, easy to integrate, often as a computer memory to make the original. For example: The memory of the PC, SDRAM, DDR, DDR2, DDR3, etc., disadvantage: Due to periodically refresh the storage media, access speed is slow.

SRAM: It is a memory with a static access function, it can save the data stored in it without needing to refresh the circuit. Therefore, its access speed is fast, but large size, power consumption, high cost, commonly used for storage capacity is not high, but fast access, such as the CPU L1 Cache,l2cache (first level, level two cache), register.

Because of the price and storage limit, mini2440 as memory is the DRAM, from the see, only bank6,bank7 to pick up the DRAM, then I guess the memory controller bank6,7 controller corresponding register must have a control refresh part, Several others do not have it because they do not need it. And then see how the memory chip on the mini2440 is wired to 2440, it uses 2 16-bit wide SDRAM:

　　

From the point of view, the chip includes the most basic address lines, data lines, compared to 2 chips, found that their same address line is connected together, are a0-a12, a total of 13 address lines, and the data line is connected to 2440 LDATA0---LDATA15, One is ldata16-ldata31, and then look at the 2440 pin:

As can be seen, 2440 of the data line is DATA0-DATA31, can receive the data width is 32 bits, and its address line is addr0--addr26, altogether is 27, then 2^27 is 128M, exactly is the memory controller a bank size. Then contact SDRAM and 2440 of the wiring, found that the data line 32 are connected by 2 chips, 2 chips respectively with 16, and the address line only used 13, 2^13=8k, how can it be addressed 128M? Furthermore, the SDRAM is actually starting from the LADDR2 wiring. Then you have to look at the SRAM manual to see how it is addressed.

　　

MINI2440 SDRAM model is H57V2562GTR, is a 256Mb 16-bit wide dram, note here is 256Mb, is small B, all in total is 256/8=32MB. Look at the structure functional block diagram of the SDRAM interior:

The memory unit of this DRAM is first composed of 4 units called Bank, then each bank unit is composed of a storage matrix, the XY axis is positioned to the smallest address granularity of a unit, that is, a 16bit storage unit. Then the data in this 16bit unit is placed on the data output port. For example, suppose a dram is an Excel file, then its bank is a sheet of Excel, by the horizontal axis (ABCDEF ...). and ordinate (12345 ...) locate a basic cell, which is the basic storage unit of DRAM, which is 16 bits wide and all basic storage units are 16bit. In the lower left corner of the address buffers,a0-13, addresses line, Ba1-ba0,bank selection line, first through the chip select the signal CS selected this chip, and then by ba[0,1] Select the bank, and then send the row address on the A0-A12, then issue the column address, The smallest addressable granularity of the storage unit is located, how to know the address line is the line address or column address it? Through RAS and CAS these 2 signal lines. Then now calculate how the 128MB, row 13, column 13,bank 2, so 2^13*2^13*2^2 = 2^28 and then 16-bit width and then multiply 2, that is 2^29MB,521MB, how a piece of more than 2440 of the addressing range, it must have been mistaken, A closer look at the introduction of DRAM:

Originally only the line address with 13 bits, the column address only used 9 bits, then by the calculation is 2^ (13+9+2+1) =32MB, and chip specifications consistent, then this explanation is reasonable. 2440 How to use the 2-block SDRAM? First to determine a few conditions, 2440 of the actual capacity of the chip itself is 4G, the address range of the storage controller is 0x00000000-0x40000000, total 1G, this 1G is divided into 8 banks, each bank 128MB, formula expression is: ADDR = 22 * 23 * 227

But this is addressed to the SDRAM to get the data is 16bit, so with 2 pieces together, one to store low 16 bits, a storage height of 16 bits. Suppose the address is 0x30000000, addressing how does it get the contents of this storage unit? First it is within the range of 1G, then again in Bank6,bank0, row 0, column 0.

This shows that only 30 bits are needed to locate an access cell, which is why the 2440 address line is only connected to the SDRAM at the beginning of the A2, since 2440 of the storage controller can only be accessed at 4byte each time. The 4 bytes of an int are stored on 2 chips, and then 4byte of data is read to the storage controller, and the lowest 2 bits of the address are not used in the storage controller to decide which byte to use. This is the addressing process for a byte.

2440SDRAM can use a 16-bit wide 2-piece stitching, or 8-bit 4-piece stitching, 32-bit 1-piece. Obviously if it is 2, the size of the 2 pieces must be the same big, or more will only be able to save 16bit, the other bits will be lost, 4 is the same.

H57v2562gtr,sdram Pin Description

External takeover pin Name	Internal takeover pin Name	Full Name	Describe
A2~a14	A0~a12	Address	Address line
D0 ~d31	Dq0~dq31	Data Input/output	Data cable
A24,a25	Ba0,ba1	Bank Address	L-bank Chip Selection Signal
Dqm0~dqm3	LDQM, UDQM	Data Input/output Mask	High, low-byte data mask signal
SCKE	SCKE	Clock Enable	Input clock active signal
SCLK	SCLK	Clock	Input clock
NSCS0	NSCS	General Chip Select	Chip selection signal (it is two functions of the same pin as the nGCS6)
Nsras	Nsras	Row Address Strobe	Line Address Select communication number
Nscas	Nscas	Column Address Strobe	Column Address Select communication number
Nwe	Newnwe	Write Enable	Write a valid signal

See 2 SDRAM and 2440 wiring can be seen, they only the data pin and LDQM UDQM pin different, these 2 pins to determine the data pin high 8-bit and low 8-bit validity, because the 2440 memory controller can only emit 4byte aligned data to SDRAM ( The connection to the data line is fixed), what if I just want to store or read a byte? Controlled by these 2 pins, it determines the validity of the 16-bit wide 8-bit, ensuring that the byte content does not change.

Reference from:

http://blog.csdn.net/mr_raptor/article/details/6555786

The SDRAM analysis of mini2440