The inout of Verilog

Source: Internet
Author: User

The data signal of the inout type.

When the write operation is valid (rd_wr_l=0): The data port input signal, at this time data is a high impedance state, allowing it to be assigned value.

When the read operation is valid (rd_wr_l=1): The data port output signal, the data assignment value Data_o,data_o is the output value.

When the chip selection signal CS is invalid (Cs=1): The data port should also be set to a high-impedance state.

Assign data = (!cs_l && rd_wr_l)? Data_o:8 ' BZ;

The inout of Verilog

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