The principle of SDRAM operation

SDRAM (Synchronous dynamic Random Access Memory, synchronous dynamically random memory) is what is commonly called memory. In the PC we use now, the memory referred to is, in fact, SDRAM, but it is his upgraded version, such as DDR memory, DDR2 memory, DDR3 memory, and so on, most graphics card on the video memory is also SDRAM.

Memory is the execution space of the code, take the PC as an example, the program is stored in the form of a file in the hard disk, the program is loaded into memory by the operating system before running, because RAM (random access memory), can locate a byte of data through the address, The CPU sets the value of the PC to the starting address in the program's storage when executing the program. CPU will be in turn from the memory of the address, decoding, execution, in memory is not initialized before, memory is not built good house, is not able to read and store data, so we want to let the program run in memory must be initialized memory.

Before introducing how memory works, it is important to understand how storage devices are stored: Rom,ram

ROM (read-only Memory): Read-only memory, is a solid-state semiconductor memory that can only read the stored data beforehand. The characteristic is that once the data is stored, it can no longer be changed or deleted. Often used in electronic or computer systems that do not need to change data frequently, data is not lost due to power off. such as: The BIOS inside the PC.

RAM (Random access Memory): Random access memory, the contents of a storage unit can be taken out or deposited on demand, and the speed of access is independent of the storage cell location of the memory. As you can see, when you give a random, valid access address, RAM returns its stored content (random addressing), and its access speed is independent of the address. This memory loses its storage content when it loses power, so it is mainly used to store random access programs in a short time. The memory address in the computer system is a four-byte aligned address (32-bit machine), the CPU's fetch, execute, and store are all through the address, so it can be used to do memory.

RAM is designed differently by hardware, and random memory is divided into dram (dynamic RAM) and SRAM (static RAM) random memory.

DRAM: Its basic original is small capacitance, capacitor can be in the two plate for a short period of time to retain the charge, can pass between the two poles have no voltage difference between 0 and 1 of the computer, due to the physical characteristics of the capacitor, to regularly charge for it, otherwise the data will be lost. The charging process of the capacitor is called refreshing, but the production process is simpler, small in size, easy to integrate, and often made as the original memory in the computer. For example: PC memory, SDRAM, DDR, DDR2, DDR3, and so on, disadvantage: Because to periodically refresh storage media, access speed is slow.

SRAM: It is a static access function of memory, do not need to refresh the circuit that can save the data stored inside it. Therefore, its access speed, but large, large power consumption, high cost, commonly used for storage capacity is not high, but fast access to the occasion, such as CPU L1 Cache,l2cache (first level, level two cache), registers.

In order to meet the needs of development, jz2440 shipped three storage media at the factory:

(1) NOR FLASH (2M): ROM memory, usually used to save bootloader, boot system boot

(2) NAND FLASH (256M, model is different, nandflash size is different): Save the operating system image file and file system

(3) SDRAM (64M): Memory, executing program

NOR FLASH: It features support for XIP-chip execution (execute in place) so that applications can run directly in Flash flash memory without having to read the code to the system RAM, which means it can be randomly addressed. NOR Flash has a higher cost.

NAND FLASH: It provides extremely high unit densities, can achieve high storage density, and writes and erases quickly. Its cost is low, does not support XIP. Can do embedded in the data storage media. such as: cell phone memory card, SD card and so on.

s3c2440 address space:

s3c2440 out of 27 address line addr0~addr26, which can be addressed to 128MB, and s3c2440 addressing space can reach 1GB, this is because s3c2440 1GB address space into 8 banks (BANK0~BANK7), Each one of the bank corresponding to a slice of the signal line NGCS0~NGCS7, when access to bankx, NGCSX pin level down, used to select foreign equipment, s3c2440 through 8 selection of signal lines and 27 address lines, you can access 1GB. As shown in the following illustration:

SDRAM storage structure:

Let's begin by introducing a set of CPU-supplied signals for SDRAM:

1. SDRAM clock effective signal scke;

2. SDRAM clock signal sclk0,sclk1;

3. Data mask signal dqm0,dqm1,dqm2,dqm3;

4. SDRAM selection Signal nSCS0 (it is the same pin with nGCS6 two functions);

5. SDRAM line address selective pulse signal nsras;

6. SDRAM column address Select pass pulse signal nscas;

7. Write Allow signal nwe (it is not dedicated to SDRAM).

The interior of the SDRAM is a storage array, arrays are similar to tables, with rows and columns, so that we have to access (read, write) a unit, we have to specify a row address, a column address, so that the unit is found, which is the basic principle of SDRAM addressing. The units here are commonly called storage units, and the entire table is called the Logical Bank (Logical Bank, L-bank), and in general each SDRAM has 4 L-bank. The logical structure of SDRAM is shown in the following illustration:

JZ2440 is the choice of 2 pieces of hy57v561620ftp-h composed of 64MB, 32-bit memory, 32MB capacity per piece, 16-bit data bus. The schematic diagram is as follows:

As you can see in the diagram, row address, column address common address line addr2~addr14 (BANK6 bit width is 32,addr0, 1 is not used), use Nsras, nscas two signals to differentiate them. In the jz2440 Development Board, use two address line ADDR24, ADDR25 as the L-bank selection signal, SDRAM chip k4s561632 row address number of 13, column address number of 9, so when the Nsras signal is valid, addr2~ ADDR14 on the line address signal, which corresponds to the 32-bit address space bit[23:11], when the NSCAS signal is valid, ADDR2~ADDR10 emits the column address signal, which corresponds to the 32-bit address space bit[10:2].

Focus on the SDRAM chip k4s561632 address line A0~A12 Description:

Each bank of the chip has 13 rows (RA0~RA12), 9 columns (CA0~CA8), row addressing using A0~A12, column addressing time-sharing multiplexing, only using CA0~CA8. NRAS, NCAs pins, which are used to identify whether the current row or column addressing, so that the address line to achieve time-sharing.

jz2440 Development Board is composed of two 16-bit SDRAM chip in parallel to form a 32-bit width, and CPU 32 data line data0~data1 connected. SDRAM is connected to the BANK6, the starting address is 0x30000000, so the access address of SDRAM is 0X30000000~0X33FFFFFF, the size is 64MB.

Look at the above content, there are some things that I can not think of the solution, may be too stupid, but finally I want to understand.

1, why two SDRAM chip in parallel, the capacity size is 64MB.

The reason is this: SDRAM Chip has 4 bank, each bank row address number is 13, row address number is 9, by two 16 bits of SDRAM chip in parallel composed of 32 bit width, and CPU 32 data line data0~data1 connected. Then its storage space is (2^13*2^9*4*32bit)/8 = 2^26*8BIT/8 = 2^26 Byte = 64MB

2, why the SDRAM chip A0 address pin is connected to the ARM chip A2 pin it.

According to the previous question, the SDRAM storage space for the 64mb,s3c2440 to address 64MB requires 26 root addresses. It is known from the schematic diagram that the SDRAM data bus has a bit width of 32 bits, that is, 4 bytes of data transmission at a time. Therefore, we can understand that an address space in fact corresponds to 4 bytes of data , in fact, the real addressing space is only 16MB, only 24 address lines (line address line 13, column address line 9, as well as L-bank Select the signal A24, A25 two root address line, A total of 24) is enough, this s3c2440 end does not need to connect all 26 address lines to the SDRAM chip, only need to give a high 24-bit address (a2~a25), equivalent to the data bus on each transmission of 4 bytes, the address space of the third (A2) increased by 1, That is, A0 and A1 can not be answered. At this point the A0 and A1 should be low level. The SDRAM chip then finds the corresponding address space according to the row address, the column address and the L-bank selection signal given by s3c2440, and sends 4 bytes of the address space to the data bus. And so on, the data bit width is 8 bits, the A0 of the arm chip is connected with the a0,16 bit of the SDRAM to A1 a0,32 bit A2 to connect A0.

There is also a detail, that is why the SDRAM chip BA0~BA1 connection is the s3c2440 chip laddr24~laddr25 pin.

Because, hy57v561620 32MB SDRAM chip, we know, 32MB storage space is required 25 address line addressing, because the BA0~BA1 pin determines the access to the first few bank, that is, the maximum storage space of two bits, therefore, You need to use the top two bits of the 25-s3c2440 address line to connect BA0~BA1 so that you can meet the mapping requirements for addressing.