The problem of series resistance on high frequency bus

In fast circuits, the project Master often recommends adding 33ω series resistors on the fast bus for three reasons:

• For impedance matching
• can reduce the voltage fluctuation and ringing effect, reduce the edge of the signal steep degree, reduce high-frequency noise and overshoot
• Also easy to debug

I use the clock frequency 50MHz when I debug DSP6713 to access the SDRAM bus.

The first PCB version number using the 0ω series resistor, test SDRAM no problem, but the second version of the PCB using 0ω found EMIF clock waveform anomalies, read SDRAM data also error. Error waveforms such as the following:

Clock waveform rendering as seen in the result is: Originally a clock rising edge, because of the fluctuation of voltage, the clock has a plurality of rising edge (such as), it will cause the original sample of the place into multiple samples, timing is wrong.

Coupled with the 33ω series resistor, the clock waveform becomes smooth, for example.

This shows that the addition and the addition of a series of resistance to the signal still has an impact! It is recommended to add a series of resistance on the fast clock bus.

the principle of the series resistor smoothing signal is the RC high frequency filter circuit .

Because the edge of a signal is assumed to be very steep, contains a large number of high-frequency components, will be radiated interference, in addition, easy to produce overshoot. The resistor in series, along with the distribution capacitance of the signal line and the input capacitance of the load, forms an RC circuit, which reduces the steep edge of the signal.

We know that the cutoff frequency of the RC circuit is F = 1/(2π* (RC) ^ (1/2)), so the values of R and C are not too large, depending on experience, it is usually best to select 33ω or 22ω.

The problem of series resistance on high frequency bus