The thinking of memory hierarchy structure and cache caching

First, we give a pyramid chart of memory:

L0 register regs. (CPU can be accessed within a clock cycle)

L1 cache SRAM several clock cycles

L2 Cache SRAM Dozens of to hundreds of cycles

L3 Cache SRAM L1, L2,L3 level three cache

L4 main main memory. Mainly made of DRAM.

L5 Local level Two storage is primarily a local disk and can be viewed as a local cache of remote storage, such as network data

L6 Remote Level Two storage (Distributed file system, Web server)

From top to bottom, the CPU's access speed is reduced in turn, and the storage capacity becomes larger.

Take an example of the Intel Core i7 cache hierarchy, assuming there are four cores, core0 ... core3, each kernel has a separate regs,l1 d-cache, L1 I-cache, a L2 unified cache, and then in the processor package, The four cores share a L3 unified cache, which is shared by all cores.

How to write cache-friendly programs. Considering the two criteria of spatial locality and time locality, when the multidimensional array is operated, the spatial locality requires the loop to be in line first, and the reference mode with step 1 is cache friendly, because the memory model of multidimensional array is linear distribution, so the cache hit will be high.
Introduction to the concept of cache cold:

In the initial access to data, the K layer of the k+1 layer of the cache is empty, at this time any k+1 layer data access will not hit, in the repeated storage makes cache warmed up after the return to normal. Typical cache structure:

(s,e,b,m) indicates that there is a cache set of S, which is the number of groups, and each group consists of E cache lines (cache line), and the data block in each row has a B byte size. The number of digits of the address represented by M. on the concept of cache jitter:

For each group has only one row of cache, the cache repeatedly loaded and replaced the same cache line phenomenon, because some data is insinuate to the same cache line, that is, the index of the cache group is the same, resulting in every time the data block, the conflict does not hit. There is also a situation, generally a cache line will have 32B or 64B, if there is an array of four double elements, four threads modify the value of the corresponding array elements, then each reference to one of the four elements may cause cache jitter, Because 4 elements are cached together in a cache line, one thread modifies one element at a time, but when other threads reference other elements, the same cache line is referenced, and the cache line is modified. In other words, the data block corresponding to the page is dirty, then it will cause the page writeback (write-back), dirty pages back to write, overwriting the cache line, so repeated operations, and constantly caused page writeback, cache repeatedly loaded and replaced the same cache line, Then performance drops, this phenomenon is called cache jitter.

about cache Read and write operations:

READ: First in the cache to find the desired word w copy, if the cache hit, then immediately return the word to the CPU, if the cache miss, then from the lower layer of memory to read out the block containing the word w, the block stored in a cache line, may overwrite a possible row.

Write: When the cache of the current layer updates w copy, how to lower the memory of the copy,1) Write-through 2 write-back-----> Mark Dirty Bit