Ti c66x DSP system events and Its Application-5.1 (configuration of QM accumulator)

The following describes how to set event and interrupt ISR in a detailed application. Taking the queue monitoring interruption (not excep) of QM as an example, it mainly includes configuring QM accumulator (used to monitor QM Queue) and ISR (ISR and event configuration ).

First, we will introduce the configuration of QM accumulator. In the Qm module, QMSs (including QMSs TX queue 800: 831, TX/RX channel 0: 31, rxchan, txchan, and TX queue are one-to-one, for example, if the Tx queue is 806, the corresponding txchan and rxchan numbers are both 6) for CPU communication. QMSs RX queue can be configured as high priority queue (General queue can also be configured ), then, use the pdsp channel (, which corresponds to the chip-event allocated to Qm, see section 5.2 of the Qm User Guide) to monitor QMSs RX queue. when conditions are met, this will cause an interruption. The TX queue of QMSs is the only input port (queue 800: 831) provided by QMSs. After a descriptor pushes to the Tx queue of QMSs, after the Tx channel and Rx channel, the output result is output to the RX queue configured for QMSs.

The configuration of QM accumulator mainly includes the QMSs RX channel enabling (only required for RX channnel), TX channel enabling and configuration, RX flow configuration, and TX Scheduler configuration, pdsp monitoring configuration. This section describes the configuration of QMSs RX channel, TX channel, and TX scheduler. The configurations of pdsp monitoring are described in section 5.2. The following describes how to create a new version of the system.

QMSs RX Channel Configuration:

Confregptr = (void *) 0x02a08800;
/* Enable RX channel */
Confregptr [Channel]. channelctrlrega = 0x80000000; // the channel is the corresponding channel of qmsstx queue.

QMSs TX Channel Configuration:

/* Configure TX channel */
Confregptr [tmpchan]. channelctrlregb = (u32) filterepi <30) | (u32) filterps <29) | (u32) aifmode <24 ); // filterepi = filterps = aifmode = 0
/* Set channel priority */
If (prioregptr! = Glo_null)
{
Prioregptr [tmpchan] = (u32) priority; // prioregptr = 0x02a08c00 (TX scheduler config). Priority = 1
}
/* Enable TX channel */
Confregptr [tmpchan]. channelctrlrega = 0x80000000;

The QMSs configuration register address (infra1 column, which is the register used by nycraftsmanship) is as follows:

RX channel a register:

TX channel B register (register a is the same as RX channel ):

TX scheduler register: