Timequest Study of Black Gold Power (iv)

Now we know that the timing constraints are mainly FPGA to IC, or IC to FPGA.

It can represent FPGA to IC and IC to FPGA.

Fpga2ic:
Fpga2ext is the route delay of IC signal caused by FPGA;
CLK2FPGA is the line delay of the clock signal to FPGA;
Clk2ext is the line delay of the clock signal to FPGA;
Tsu/th The register characteristics of the external device;
(Tsu signal settling time; Th signal hold time)
IC2FPGA:
EXT2FPGA is the route delay of IC-induced FPGA signal;
CLK2FPGA is the line delay of the clock signal to FPGA;
Clk2ext is the line delay of the clock signal to FPGA;
Tco/mintco The register characteristics of the external device;
(Tco signal output time; Mintco min. signal output time)

First Look at Fpga2ic:

is the signal connection of the FPGA to IC. I wrote the Sram,uart and this still a little bit different because only the data line, no CLK.

The clock skew results will ultimately directly affect the delay of the data. This is a very important point. Clock skew = < destination reg Clock Delay >-< source reg Clock Delay >

For the outer model of FPGA2IC, FPGA_CLK is the source register clock, however EXT_CLK is the purpose register clock.
Data delay = 2ns
Data delay ' = <data delay>-<clock skew>
= 2ns-2ns
= 0ns
Data delay
Data delay after the clock difference action

Indicates: Data delay 2ns, that is, 2ns data to reach the destination register, that is, the settling time 8ns, but because the clock offset 2ns effect to the data offset, the equivalent of data no delay. The settling time is 10ns.

Clock offset: 2-1 = 1ns, data delay: 2ns, when the clock offset is used for data delay after the data delay time: Data_delay-clock_skew = 2-1 = 1 ns.

The above is the establishment of the relationship, the following analysis to maintain the relationship:

If you use "buttocks" to calculate the hold time: Data_arrival_time-data_aquaire_time = 2-2 =0ns.

Similarly, if you use the "butt" calculation: (1+2)-2 = 1 ns.

If Clock_skew is acting on data_delay:data_delay-clock_skew = 3-2 = 1ns.

The above is the FPGA to IC, followed by the IC to FPGA: Clock offset for data after settling time and hold time.

You can see that the FPGA is receiving data at this time, but the clock offset is the same as for the data delay principle.

This is the hold time graph. Clock_delay = 1ns;data_delay = 2ns;data_delay ' = Data_delay-clock_skew = 2-1 = 1ns.

The above discussion is a bit wide, and that is more than a bit wide?

Uniform and non-uniform delay pressure.

This has an impact on the hold time and the settling time. It can be seen from max_delay = 3ns, Min_delay = 1ns. The most dangerous establishment time is d[2] = 7ns, the most dangerous to hold time is d[0] = 1ns, you can know Max_delay impact settling time, Min_delay influence hold time. Such as:

What is the result of Clock_skew acting on uneven delays? The principle is still the same, that is, the clock is offset to the data and the clock remains the same. Such as:

Timequest Study of Black Gold Power (iv)