Tsu/TCO constraints in Quartus II

Address: http://hi.baidu.com/gmy2171/blog/item/2e3c2f890ffc4dbf0e2444cf.html

 

Tsu/TCO have two different meanings in the Quartus II report.

1. The TSU/TCO in the slice refers to the TCO of the front-Level Trigger and the Tsu of the Back-Level Trigger. Generally, the Tsu is several hundred PS level. You can view it through the "List paths" command. The TSU/TCO here is mainly determined by the device process. The temperature and voltage changes slightly during operation, as shown in)
   
2. Tsu/TCO on pins it is an important timing element (as shown in) to ensure the system famx ). for example, the two chips work at 100 MHz, because the period of 100 m is 10ns (the latency of PCB cabling is ignored). If a signal is input to FPGA, the TCO of the front-Level Chip cannot exceed 10 ns with FPGA Tsu. if a signal is output to an FPGA, the TCO of the FPGA plus the Tsu of the Back-Level Chip cannot exceed 10ns. only in this way can inter-chip communication be ensured. Therefore, it is a crucial timing design technique to make appropriate TCO/TSU timing constraints on FPGA pins.
   

The TSU/TCO on the pin is divided into the following three parts.

1. IOE cabling delay. this latency is proportional to the Tsu/TCO latency of the pin. To reduce the latency of Tsu/TCO on IOE, two types of triggers are set specifically in IOE: fast input register (TSU optimized when FPGA pins are input) and fast output register (when FPGA pins are output, used to optimize TCO)
2. Internal logical cabling delay. In FPGA of Altera, a lab is composed of several basic resources le. For example, stratixgx is a lab composed of 10 le. lab horizontal and vertical arrangement form an array. in FPGA, the basic unit of lab is divided into C4 (representing the cabling resources across four labs), C8, C16, R4, R8, 16, based on the line length, different devices support different cabling resources, such as R24.
3. Tsu/TCO requirements for triggers. tsu/TCO here is determined by the device process and the minimum Tsu/TCO requirements. in the actual working environment, the temperature and voltage changes slightly.

As mentioned above: it is a crucial timing design technique to impose appropriate TCO/TSU timing constraints on FPGA pins. The key is how to solve the problem when the problem arises?
Quartus II has four limitations on Tsu/TCO.
1. Global timing constraints. execute Assignments → timing setting in Quartus II to bring up the following interface. Designers can constrain Tsu/TCO according to the requirements of the system FMAX.

2. run the assignments → Assignment Editor command to obtain the following interface. the designer can set Tsu/TCO constraints on the input/output pins according to the requirements of this design. It can also constrain the Tsu/TCO values of internal triggers. (As shown in)

3. Execute the assignments → Assignment Editor command and select "all" or "logic options" to restrict Tsu/TCO on the pins.

Select the corresponding PIN in "to", select "fast input register" in assignment name to constrain Tsu, and select "Fast output register" to constrain TCO. this is also what logic engineers usually say: to reduce the Tsu/TCO value, put it in IOE.
3. Modify the underlying Circuit After wiring.
Execute the processing → compilation report command. In resource section → input pins/output pins, select the corresponding Input and Output pins, as shown in ).

Run the locate → locate to chip editor command. The following page is displayed.

The selected pin has been highlight (as shown in) in the chip editor. Double-click the pin of highlight to obtain the interface.

The parameters here are all the parameters after the PIN is routed. Not every parameter can be modified. for example, for the LVDS level standard, the current strength cannot be modified. for the lvttl level standard, current strength has 2, 4, 8, 16, 24mA and can be modified.
The designer can enable or disable fast input register/fast output register attribute based on the design requirements, and can modify the delay from the input pin to the logical array and the delay from the output pin to the logical array.

After the modification, you cannot program the project again. You only need to execute processing → start javaser to update the SOF and POF programming files.