Turn STM32 clock tree

This article from: http://www.openedv.com/posts/list/302.htm

Author Zhang Yang

The clock system is the core of the processor, so it is necessary to learn the clock system carefully before learning STM32 all the peripherals, which helps to understand the STM32 deeply.
Here is a STM32 clock diagram from the Internet, which looks clearer than the one in the STM32 Chinese reference manual:

Important Clocks:
The relationship between PLLCLK,SYSCLK,HCKL,PCLK1,PCLK2 to be clear;


1, HSI: high-speed internal clock signal stm32 microcontroller inner band clock (8M frequency) accuracy is poor
2. HSE: High speed external clock signal precision Source (1) HSE external crystal/Ceramic resonator (crystal oscillator) (2) HSE user external clock
3, LSE: low-speed external crystal 32.768kHz mainly provides an accurate clock source is generally used as the RTC clock


In STM32, there are five clock sources for HSI, HSE, LSI, LSE, PLL.

①, HSI is a high-speed internal clock, RC oscillator, frequency of 8MHz.

②, HSE is a high-speed external clock, can be connected to the quartz/ceramic resonator, or external clock source, frequency range of 4mhz~16mhz.

③, LSI is a low-speed internal clock, RC oscillator, frequency of 40kHz.

④, LSE is a low-speed external clock, the frequency of 32.768kHz quartz crystals.

The ⑤, PLL is a phase-locked loop multiplier output, and its clock input source can be selected as HSI/2, HSE, or HSE/2. The multiplier can be selected as 2~16 times, but its output frequency must not exceed 72MHz.

The 40kHz LSI is used by independent watchdog IWDG, and it can also be selected as the clock source for real-time clock RTC. In addition, the clock source of the real-time clock RTC can also be selected LSE, or the 128 division of HSE. RTC's clock source is selected via rtcsel[1:0].

There is a full-speed USB module in the STM32, and its serial interface engine requires a clock source with a frequency of 48MHz. The clock source can only be obtained from the PLL output, optionally 1.5 or 1, that is, when a USB module is required, the PLL must be enabled, and the clock frequency is configured to 48MHz or 72MHz.

In addition, the STM32 can choose a clock signal output to the MCO foot (PA8), you can choose to output the PLL 2, HSI, HSE, or system clock.

The system clock SYSCLK, which is the clock source for most parts of the STM32. The system clock can be selected as a PLL output, HSI, or HSE. The system clock maximum frequency is 72MHz, it passes through the AHB divider to send to each module to use, the AHB divider may choose 1, 2, 4, 8, 16, 64, 128, 256, 512 divide. Where the clock of the AHB divider output is sent to the 5 modules using:

①, a hclk clock for AHB bus, kernel, memory, and DMA use.

②, the system timer clock sent to cortex by 8.

③, the idle run clock fclk that is sent directly to cortex.

④, give APB1 divider. APB1 Divider can choose 1, 2, 4, 8, 16 divided, its output for APB1 peripheral use (PCLK1, the maximum frequency 36MHz), the other way to the timer (timer) 2, 3, 4 times frequency multiplier used. The multiplier can choose 1 or twice times, the clock output for Timers 2, 3, 4 use.

⑤, give APB2 divider. APB2 crossover can choose 1, 2, 4, 8, 16, the output of the APB2 peripheral use (PCLK2, the maximum frequency 72MHz), and the other way to the timer (timer) 1 time multiplier used. The multiplier can choose 1 or twice times, the clock output for the timer 1 use. In addition, the APB2 divider has one output for the ADC divider, which is used for the ADC module. The ADC divider can be divided into 2, 4, 6, 8.

In the above clock output, there are many with enable control, such as AHB bus clock, core clock, a variety of APB1 peripherals, APB2 peripherals and so on. When you need to use a module, be sure to first enable the corresponding clock.

Note that the timer multiplier, when the division of the APB is 1 o'clock, its multiplier value is 1, otherwise its multiplier value is 2.

The devices connected to the APB1 (low Speed peripherals) are: Power Interface, Backup interface, CAN, USB, i2c1, I2C2, UART2, UART3, SPI2, window watchdog, Timer2, Timer3, Timer4. Note that the USB module requires a separate 48MHz clock signal, but it should not be a clock for the USB module to work, but simply a clock to be used by the serial Interface Engine (SIE). The clock that the USB module works on should be provided by APB1.

The devices connected to the APB2 (high-speed peripherals) are: UART1, SPI1, Timer1, ADC1, ADC2, all normal IO ports (PA~PE), and the second function IO port.


Registers involved:
The RCC register structure, Rcc_typedeff, is defined in the file "Stm32f10x_map.h" as follows:
typedef struct
{
Vu32 CR; HSI,HSE,CSS,PLL and so on to enable
Vu32 CFGR; Clock source selection and crossover factor setting for PLL, etc.
Vu32 CIR; Clear/Enable clock ready interrupt
Vu32 Apb2rstr; APB2 on-line Peripheral Reset Register
Vu32 Apb1rstr; APB1 on-line Peripheral Reset Register
Vu32 Ahbenr; Dma,sdio, etc. clock enable
Vu32 Apb2enr; APB2 on-line peripheral clock enable
Vu32 Apb1enr; APB1 on-line peripheral clock enable
Vu32 BDCR; Backup Domain control Register
Vu32 CSR;
} rcc_typedef;

You can learn about the upper clock block diagram and the RCC register, have a ballpark understanding of the STM32 clock system, and then study with the system clock configuration function void Stm32_clock_init (U8 PLL) of our STM32 incomplete manual.

Turn STM32 clock tree