Two design methods of InOut port in Verilog

When we learned about IIC, we knew the design was inout.

InOut SCL;

Reg Scl_reg, scl_en;

SCL = scl_en? Scl_reg:1 ' dz;

When scl_en effectively outputs the waveform of Scl_reg, it is output, otherwise it is input.

Later in the work encountered a IIC IP core, this IIC IP core interface is such a sub-

1 mi2c U_MI2C (2         . CLK (clock),3         . NRST (reset),4         . A (a),5         . Di (DI),6         . WR (WR),7         . SEL (SEL),8         . ISCL (ISCL),9         . ISDA (ISDA),Ten . Da (DA), One         . NOE (NOE), A         . INTR (INTR), -         . OSCL (OSCL), -         . OSDA (OSDA) the);

In this IP, the IIC input and output are separated. And there is no scl_en to make the above mentioned. This I am ignorant, after a painstaking search, finally know how to merge, nonsense not much to say, directly on the code, and finally become this look.

1 ModuleMi2c_top (2 Clock,3 Reset,4 A,5 di,6 WR,7 SEL,8 SCL,9 SDA,Ten da, One Noe, A Intr -                 ); - inputclock, reset; the input[2:0] A; - input[7:0] di; - inputWR, SEL; -  + Output[7:0] da; - OutputNoe, intr; +  A inout Tri1SCL; at inout Tri1SDA; -  -  WireISDA,ISCL,OSDA,OSCL; -  - mi2c U_MI2C ( -         . CLK (clock), in         . NRST (reset), -         . A (a), to         . Di (DI), +         . WR (WR), -         . SEL (SEL), the         . ISCL (ISCL), *         . ISDA (ISDA), $ . Da (DA),Panax Notoginseng         . NOE (NOE), -         . INTR (INTR), the         . OSCL (OSCL), +         . OSDA (OSDA) A         ); the          + AssignISCL =SCL; - AssignISDA =SDA; $ AssignSCL = (OSCL = =1'd0)? 1'D0:1'DZ; $ AssignSDA = (OSDA = =1'd0)? 1'D0:1'DZ;  -          -          the Endmodule 

In the Modelsim simulation can be seen, if the high level, will show a dashed line, that is, the meaning of the weak pull-up.

Little friends, no longer have to worry about inout mouth.

Two design methods of InOut port in Verilog