Understand "unified addressing and independent addressing, I/O port and I/O memory"

Introduction:

A line is connected from the CPU: Data Bus, address bus, and control bus. N interfaces are hung online, which have the same and different interfaces, it is called memory interface, interrupt control interface, DMA interface, parallel interface, serial interface, AD interface ...... To connect a device to IOT platform, you must use your own interface to connect to a certain online interface ...... So there are various devices on the Bus: memory, hard disk, mouse, keyboard, display ......

For the CPU, if it wants to send data to a device, it actually sends data to the corresponding interface. The interface circuit contains multiple registers (also called ports ), the access device actually accesses the relevant port, and all the information will be transferred from the interface to its device. So the CPU will prepare data to the data bus, but who should I send many interfaces? In this case, you need to allocate an address for each interface, and then place the address on the address bus. The required control information is placed on the control bus to communicate with the device.

For a system, there are usually multiple peripherals. There are multiple ports in each peripheral interface circuit. Each port requires an address to identify a specific address value for them, the system must solve the problem. At the same time, you still have a memory stick, which may be m or 1g or larger Kingston, modern DDR2, and so on. Each of their addresses also need to be assigned an id value, in addition, many peripherals have their own memory and buffer. Just like your memory, you also need to allocate memory for them ...... Your CPU may have to deal with every byte of them, so do not expect to be lazy. plan every inch of their land! This sounds annoying, and it may directly cause all brain cells to be killed. However, some people always have to do things, and arm may do this: the CPU he designed this time is 32-bit, so it can address up to 2 ^ 32 = 4g space, therefore, we threw the 4 GB space to the memory and port to split them up. But intel may have a better way to allocate ......

(1) concept of address

1) physical address: the address sent from the CPU address bus, which is controlled by the hardware circuit. A large part of the physical address is left to the memory in the memory, but is often mapped to other memory (such as video memory and BIOS ). After the virtual address in the program instruction passes the field ing and page ing, a physical address is generated, which is placed on the address line of the CPU.

The physical address space is used by the physical RAM (memory) and the bus. This is determined by the hardware design. Therefore, in the x86 processor of the 32 bits address line, the physical address space is 2 to the power of 32, that is, 4 GB, but physical Ram generally cannot reach 4 GB, because there are still some to be used for the bus (there are many other devices hanging on the bus ). In PCS, low-end physical addresses are generally used for ram, and high-end physical addresses are used for bus.

2) BUS address: the BUS address line or signal generated during the address cycle. The peripherals use the BUS address and the CPU uses the physical address.

The relationship between the physical address and the BUS address is determined by the system design. On the X86 platform, physical addresses are bus addresses because they share the same address space. This is a bit difficult to understand. For details, see the "independent addressing" section below ". Conversion/ ing may be required on other platforms. For example, if the CPU needs to access a unit whose physical address is 0xfa000, an access to the 0xfa000 address on the PCI bus will be generated on the X86 platform. Because the physical address is the same as the BUS address, it cannot be determined by your eyes where the address is used, whether it is in memory or a storage unit on a card, it is even possible that there is no corresponding storage on this address.

3) Virtual Address: Virtual Memory Management (vmmemory management) is widely used in modern operating systems. This requires the support of MMU (Memory Management Unit. MMU is usually a part of the CPU. If the processor does not have MMU, or MMU is not enabled, the memory address sent by the CPU Execution Unit will be directly transmitted to the Chip Pin, by the memory chip (physical memory) receiving, which is called the physical address (physical address). If MMU is enabled for the processor, the memory address sent by the CPU Execution Unit will be intercepted by MMU, the address from CPU to MMU is called virtual address, and MMU translates this address into another address and sends it to the external address pin of the CPU chip, that is, the virtual address is mapped to a physical address.

In Linux, the 4 GB (virtual) memory of a process is divided into user space and kernel space. User space distribution is 0 ~ 3 GB (that is, page_offset, in 0x86, It is equal to 0xc0000000)

And the remaining 1 GB is the kernel space. Programmers can only use virtual addresses. Each process in the system has its own private user space (0 ~ 3G), this space is invisible to other processes in the system.

When the CPU sends a request to fetch commands, the address is the virtual address of the current context. MMU then finds the physical address of the virtual address from the page table to complete the retrieval. A virtual address is used to read data, such as mov ax and var. during compilation, VaR is a virtual address. It also uses MMU to find the physical address from the table, and then generates the bus sequence to get data.

(2) Addressing Method

1) peripherals are all performed by reading and writing registers on the device. The peripherals register is also called "I/O port", and the IO port has two addressing methods: Independent addressing and unified compiling.

Unified addressing: the I/O registers (I/O Ports) in the peripheral interfaces are the same as those in the primary storage unit. Each port occupies the address of a storage unit and is allocated as an I/O address space, for example, in the PDP-11, the highest 4 K main memory as the IO Device Register address. The port occupies the address space of the memory, reducing the storage capacity.

The unified addressing is also called the "I/O memory" method. The peripheral registers are located in the "memory space" (many peripherals have their own memory and buffer zone, the registers and memory of peripherals are collectively referred to as "I/O space ").

For example, Samsung's S3C2440 is a 32-bit ARM processor whose 4 GB address space is divided by peripherals and ram:

0x8000 1000 led 8*8 lattice address

0x4800 0000 ~ 0x6000 0000 SFr (special temporary storage) Address Space

0x3800 1002 keyboard address

0x3000 0000 ~ 0x3400 0000 SDRAM Space

0x2000 0020 ~ 0x2000 002e ide

0x1900 0300 CS8900

Independent addressing (separate addressing): the IO address and the storage address are separated and the I/0 port address does not occupy the address range of the storage space. In this way, there is another IO address unrelated to the storage address in the system. The CPU must also have Io commands (In, out, etc.) and control logic dedicated to input/output operations. Under an independent address, the address bus has an address. The device does not know whether it is for the I/O port or for the memory, therefore, the processor uses memr/memw and IOR/Iow control signals to address the I/O port and memory differently. For example, intel X86 uses a separate address, and the CPU memory and I/O are co-located. That is to say, some of the memory addresses overlap with I/O addresses.

The independent address is also called the "I/O port" mode, and the peripheral registers are located in the "I/O (Address) Space ".

For the X86 architecture, access through the in/out command. The PC architecture has a total of 65536 8-bit I/O ports, which constitute 64 k I/O address spaces, numbered from 0 ~ 0 xFFFF, there are 16-bit, 80 x86 with a low 16-bit address line A0-A15 to address. Two 8-bit ports can form a 16-bit port, and four in a row form a 32-bit port. The I/O address space and the physical address space of the CPU are two different concepts. For example, the I/O address space is 64 KB, and the physical address space of a 32bit CPU is 4 GB. For example, you can see in "More/proc/ioports" under intel 8086 + redhat9.0:

2017-001f: dma1

0020-003f: pic1

0040-005f: Timer

0060-006f: keyboard

0070-007f: rtc

0080-008f: DMA page Reg

00a0-00bf: pic2

00c0-00df: dma2

00f0-00ff: FPU

0170-0177: ide1

......

However, the intel X86 platform generally uses a technology called memory o ing (mmio), which is part of the PCI specification. After the I/O device port is mapped to the memory space, the CPU accesses the I/O port just like the memory. See the typical Memory Address Allocation Table for x86/x64 systems in Intel ta 719 documents:

System resource usage

------------------------------------------------------------------------

BiOS 1 m

Local APIC 4 K

Chipset reserved 2 m

Io APIC 4 K

PCI device 256 m

PCI Express device 256 m

PCI device (optional) 256 m

Show frame cache 16 MB

Tseg 1 m

For an established system, it is either an independent address or a unified address. The specific method depends on the CPU architecture. For example, PowerPC and m68k adopt uniform addressing, while x86 adopt independent addressing, which has the concept of Io space. Currently, most embedded microcontroller such as arm and PowerPC do not provide I/O space. They only have memory space and can be accessed directly using addresses and pointers. But for Linux kernel, it may be used for different CPUs, so it must consider both methods, so it adopts a new method, i/O port based on I/O ing or memory ing is called "I/O Region" (I/O Region), no matter which method you use, you must first apply for the IO region: request_resource () and release it at the end: release_resource ().

2) Access to peripherals

1. The process for accessing the I/O memory is: request_mem_region ()-> ioremap ()-> ioread8 ()/iowrite8 ()-> iounmap ()-> release_mem_region ().

As mentioned above, I/O memory is the concept of uniform addressing. For uniform addressing, I/O address space is part of the physical master memory. for programming, we can only operate on virtual memory, the first step is to map the physical address of the device to a virtual address. ioremap () is used in linux2.6 ():

Void * ioremap (unsigned long offset, unsigned long size );

Then, we can directly access these addresses through pointers, but we can also use a set of functions in the Linux kernel to read and write:

Ioread8 (), iowrite16 (), ioread8_rep (), iowrite8_rep ()......

2. Access the I/O port

There are two ways to access the IO port: I/O ing (I/O-mapped) and memory ing (memory-mapped ). In the previous approach, functions such as intb ()/outb () are directly used to read and write Io ports without being mapped to the memory space; the latter type of mmio maps the I/O port to the I/O memory ("memory space"), and then uses the function to access the I/O memory to access the I/O port.

Void ioport_map (unsigned long port, unsigned int count );

Using this function, you can map the Count consecutive Io ports starting with port to a "memory space ", then, you can access these I/O ports at the returned address just like accessing the I/O memory.

I/0 independent addressing has the following advantages: no memory space is occupied; I/O commands are used, and the program is clear, so it is easy to see whether it is an I/O operation or a memory operation; the decoding circuit is relatively simple (because the address space of the I/0 port is generally small, and the address line is less ). The disadvantage is that only dedicated I/0 commands can be used. There are more methods to access the memory than to access the port.
Which of the following depends on the overall system design. Two methods can be used in a system, provided that I/O independent addressing is supported first. : Intel x86 microprocessor supports independent I/O addressing, because their instruction systems contain I/O commands, and set control signal pins that can distinguish I/O access from memory access. Some microprocessor or single-chip microcomputer, in order to reduce the pin, thus reducing the occupied area of the chip, do not support I/O independent addressing, can only use unified memory addressing.