Since uClinux can only run on the core, it provides support for the B core in the form of a driver. By default, this feature is enabled. You can disable it through kernel settings-> Blackfin Processor options-> bf561 specific configurations-> core B support. It is estimated that no one will do this, right? Haha !. All of the following code comes from: linux-2.6.x/ARCH/Blackfin/mach-bf561/coreb. C, that is, the/dev/coreb driver implementation file.
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, Driver status viewIf the driver is correctly loaded, the following prompt is displayed when the system starts: bf561 core B driver v0.1 initialized. You can see the running status of the driver through the following command: Root: ~> CAT/sys/class/MISC/coreb/coreb_statusbase address: 0xff600000core B is unsupported: Unknown: 0020 IRQ status: core a core bisr0: 00000000 bytes specified isr1: 00000000 bytes specified imask0: 30000000 bytes specified imask1: 008a8000 00000000
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, Driver-implemented FunctionsLet's take a look at the functions implemented by this driver. Static struct file_operations coreb_fops = {. owner = this_module ,. llseek = coreb_lseek ,. read = coreb_read ,. write = coreb_write ,. IOCTL = coreb_ioctl ,. open = coreb_open ,. release = coreb_release}; static struct miscdevice coreb_dev = {coreb_minor, "coreb", & coreb_fops}; execute the bf561_coreb_init function when loading this module. This function has a piece of code: misc_register (& coreb_dev); If (class_device_create_file (coreb_dev.class, & class_device _ Attr_coreb_status) goto release_dma_src; the two lines of code register the driver information with the kernel. From this information, we can see that the device can be turned on and off. Fread and fwrite can be used to read and write data. fseek can be used to locate pointers and IOCTL can be used to control input and output. We can see from the above that the processing of IOCTL calls is completed by the coreb_ioctl function, as shown below: // define the commands available in The IOCTL call # define 1__coreb_index 1 # define 1__coreb_start 2 # define 1__coreb_stop 3 # define 1__coreb_reset 4 static int coreb_ioctl (struct inode * inode, struct file * file, unsigned int cmd, unsigned long Arg) {int retval = 0; int coreb_index = 0; Switch (CMD) {// you can specify the base address pointer and the available space, this is the base address when the file is opened for read/write. Case when _coreb_index: If (copy_from_user (& coreb_index, (int *) Arg, sizeof (INT) {retval =-efault; break;} spin_lock_irq (& coreb_lock ); switch (coreb_index) {// indicates the 0xff60 0000 ~ 0xff60 4000 reads and writes the 16 K space, that is, the L1 instruction cache in core B. When coreb starts to allow execution, the first command starts from 0xff60 0000. Therefore, you should write executable code here before allowing the B-core to run. Case 0: coreb_base = 0xff600000; coreb_size = 0X4000; break; // indicates 0xff61 0000 ~ 0xff61 4000 this 16 K address space is operated, that is, the L1 instruction cache in B core. Case 1: coreb_base = 0xff610000; coreb_size = 0X4000; break; // indicates that 0xff50 0000 ~ 0xff50 8000 this 32 K address space is operated, which is the data cache in the B core. Case 2: coreb_base = 0xff500000; coreb_size = 0x8000; break; // indicates 0xff40 0000 ~ 0xff40 8000 this 32 K address space is operated, which is another data cache in B core. Case 3: coreb_base = 0xff400000; coreb_size = 0x8000; break; default: retval =-einval; break;} spin_unlock_irq (& coreb_lock ); mutex_lock (& file-> f_dentry-> d_inode-> I _mutex); file-> f_pos = 0; mutex_unlock (& file-> f_dentry-> d_inode-> I _mutex); break; // The B-core is required to run the code case when _coreb_start: spin_lock_irq (& coreb_lock) from the 0xff60 0000 position; if (coreb_status & coreb_is_running) {retval =-ebusy; break;} printk (K Ern_info "Starting core B/N"); coreb_status | = coreb_is_running; // set coreb_sram_init in sica_syscr to 0, that is, allow B core to start executing bfin_write_sica_syscr (bytes ()&~ 0x0020); ssync (); spin_lock_irq (& coreb_lock); break; # If defined (config_bf561_coreb_reset) // requires B-core to stop running case when _coreb_stop: spin_lock_irq (& coreb_lock ); printk (kern_info "stopping core B/N"); // set the coreb_sram_init bit in sica_syscr to 1 bfin_write_sica_syscr (bfin_read_sica_syscr () | 0x0020 ); // write the cb_supplement_int0 bit in sicb_syscr to 1, and the B-core is required to generate interrupt 1. After the reset, because coreb_sram_init in sica_syscr is 1, the B-core will no longer run. Bfin_write_sicb_syscr (bfin_read_sicb_syscr () | 0x0080); coreb_status & = ~ Coreb_is_running; spin_lock_irq (& coreb_lock); break; // requires B-core reset case when _coreb_reset: printk (kern_info "resetting core B/N"); bfin_write_sicb_syscr (Issue () | 0x0080); break; # endif} return retval;} processing of read and write operations is relatively simple. Note the following: when reading and writing, the driver automatically adds the base address to the file location in the file structure before reading and writing, and the Read and Write cannot exceed the size allowed by each block. Otherwise, the read and write will fail ,. For example, the read/write throughput of 0xff60 0000 cannot exceed 4 kb.
