Use of HDL coder in MATLAB

Today, I found out how to use the HDL coder. The main steps are as follows:

1. To call Quartus or Xilinx integrated layout cabling, you must first set the method in either of the following ways: input in the Command window

Hdlsetuptoolpath ('toolname', 'altera us II ',...
'Toolpath', 'd: \ Altera \ 10.1 \ Quartus \ bin \ quartus.exe '), or find toolbox \ Local in the installation directory of MATLAB to create a startup. M writes this command in. If Quartus is used, you only need to change the path, and cylinth changes the Tool Name path (startup. m can also add other commands, Matlab will execute at startup, such as changing the default path to a frequently used address, and so on ).

2. after the directory is switched to the project directory, enter hdlcoder in the command line to start. Enter the project name, project path, and save the project. At this time, there will be a prompt box on the Right of Matlab, in two parts, function and test partition add two files respectively.

3. Click workflow advisor to go to the conversion page. I think there are three main conversion blocks: 1. Floating Point to fixed point conversion. 2. Generate the HDL file. 3. Generate the simulation file. It is better to use Quartus or Xilinx for integrated layout cabling. For sharding, 1. Run the define input types command before the floating point is converted to a fixed point. If the file is okay, the system automatically captures the input data type. Before converting a fixed point, set a fixed length. The recommended length is two. One is the decimal length, the other is the data Bit Width, that is, the length of the Register-type data after the Tilde is generated. Undoubtedly, it is recommended that the data Bit Width be selected for the fixed decimal length. It seems that there is a 4% margin in the Data Manual. If you do not go deep into it, the simulation will be performed after the simulation, during the simulation process, the software automatically captures the data range and provides a reasonable Bit Width. If you do not think it is appropriate, You can manually modify the data range. You only need to click the suggested bit width to see the dialog box change. Then, the MATLAB program is generated to indicate the number of points, and then the error of the fixed point design compared with the floating point design will be checked, and a corresponding report will be generated. Of course, the larger the bit width, the smaller the error.

4. when the switch point is completed, the HDL is generated. There are many options for generating the HDL, among which I think the most important is the optimization options, including the setting of pipeline, resource sharing, and loop expansion, however, after reading a video, people can use streaming to reduce the number of multiplier and sub-devices, but I cannot find the streaming option. I don't know if it is a version issue? (I used 2014a and 2012a for video) it is still another problem. I used the example in the user guide to find that the fpga25 multiplier is consumed if it is not too complicated, it would be better to find the optimization method. The bottleneck of Algorithm Design for Chinese source and speed lies in the multiplier. If it can be improved, the system will speed up.

5. the simulation file contains not only the HDL file, but also the cosimulation file MATLAB and Modelsim for simultaneous simulation, as well as the FPGA-in-the-loop simulation file, it is a file required for the collaborative simulation of MATLAB and FPGA hardware. It is not available yet.

6. The entire process has been taken over, but the problem persists. Further research is required.

Use of HDL coder in MATLAB