Verilog Design Advanced
Date: May 6, 2014 Tuesday
Main Harvest:
1. Write the first Verilog program yourself.
Topic:
Using a 10M clock, a single-cycle shape such as the following periodic waveform is designed.
Thinking:
The first idea is to define two counters to count and two enable flags to control the two variables separately. But this logic is too complicated, search on the internet, or the definition of a counter is better.
Verilog Program:
Modulefdivision (CLK, RST, clk_out);
Input CLK;
Input rst;
Output clk_out;
REG[5:0] Count;
Reg Rclk_out;
Assign clk_out = Rclk_out;
[Email protected] (Posedge CLK or Negedge rst) begin
if (!rst) begin
count<=0;rclk_out<=0;
End
else if (count==30)
count<=0;
else count<=count+1;
End
[Email protected] (Posedge CLK) begin
if (count<=9) rclk_out<=1;
else rclk_out<=0;
End
Endmodule
Test file:
' Timescale1ns/1ns
Modulefdivision_test;
Reg CLK, rst;
Wire clk_out;
Always #2 clk=~clk;
Initial begin
Clk=0;rst=1;
#20 rst=0;
#20 rst=1;
#500 $stop;
End
Fdivision U1 (CLK, RST, clk_out);
Endmodule
Simulation Waveform diagram:
Verilog Crossover Device