Verilog VGA Display

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Implement screen block movement using Verilog
Code is as follows:

"'" Timescale 1ns/1ps////////////////////////////////////////////////////////////////////////////////////  
Company://Engineer:////Create DATE:2017/05/12 20:29:36//Design Name://Module name:vga_test//Project name: Target Devices://Tool Versions://Description:////Dependencies:////Revision://Revision 0.01-file C reated//Additional Comments:///////////////////////////////////////////////////////////////////////////////////  /////////////////////////////////////////////////////////////////////////////////////Company://Engineer://// Create DATE:2014/09/22 22:18:12//Design Name://Module NAME:A1//Project Name://Target Devices://Tool Versio NS://Description:////Dependencies:////Revision://Revision 0.01-file Created//Additional Com ments://////////////////////////////////////////////////////////////////////////////////////640*480@60HZ, Clock pixel : 25MHZ module A1 (module vga_test (NCLK,rst_n, Hsync,vsync, VGA_R,R0,R1,R2,VGA_G,G0,G1,G2,VGA_B,B0,B1,B2);         Input NCLK;      Internal 100M clock inputs input rst_n;    Reset key output Reg Hsync,vsync;    field synchronization, line synchronization signal output VGA_R,VGA_G,VGA_B,R0,R1,R2,G0,G1,G2,B0,B1,B2;      Color signal output REG[10:0] x_cnt;        Line coordinate count, for the next row of 0 or 1 and the location of the specific pixels to prepare reg[9:0] y_cnt;              column coordinate count, for 0 or 1 of the following column and the location of the specific pixel points to prepare Reg CLK;
    Achieve the pixel frequency after 4//100m to 25M divider design reg[2:0]clk_cnt;
    REG[8:0]FLAG1;
    Reg[8:0]flag2;

    Reg[26:0]count; 
        Initial//Register variable assigns initial value begin Clk=1 ' B0;
      Clk_cnt=3 ' D0; End//red-green-blue other three ports assign R0=1 ' B0; Assign R1=1 ' B0; Assign R2=1 ' B0; Assign G0=1 ' B0; Assign G1=1 ' B0; Assign G2=1 ' B0; Assign B0=1 ' B0; Assign B1=1 ' B0;  
    Assign B2=1 ' B0; 
      Always @ (Negedge nclk) begin clk_cnt = clk_cnt + 1; 
      if (clk_cnt==3 ' D2) CLK =1 ' B1;
          else if (clk_cnt==3 ' D4) begin Clk=1 ' B0; 
         Clk_cnt=3 ' D0; End END//Achieve four//VGA display design//Pixel count always@ (Posedge CLK or Negedge rst_n) begin if (rst_n)   X_cnt=11 ' D0; 
      Reset Line coordinates 0 else if (x_cnt==11 ' d800)//line has 800 pixel point on the re-sweep x_cnt=11 ' D0;     else x_cnt = x_cnt + 1 ' B1; Scan line End//Row Count always@ (Posedge CLK or Negedge rst_n) if (rst_n) y_cnt = Ten ' D0; 
        Reset, column 0 else if (y_cnt==10 ' d525)//column has 525 pixel points on the re-sweep y_cnt=11 ' D0;
     else if (x_cnt==11 ' D800)//a row to replace a column y_cnt = y_cnt + 1 ' B1; Define screen display area wire valid = (x_cnt>=11 ' d144) && (x_cnt<=11 ' d784) && (y_cnt>=10 ' D35) && (y_ 

    Cnt<=10 ' d515); Wire [9:0] xpos = x_cnt;

    Wire [9:0] ypos = y_cnt; Row timing is determined always@ (Posedge CLK or Negedge rst_n) if (rst_n) hsync =1 ' b0;//reset starting from 0 else if (x 
        _cnt==11 ' D0) hsync=1 ' B0; 
   else if (x_cnt==11 ' d96) hsync=1 ' B1; Determination of the frame timing always@ (Posedge CLK or NegedgeRst_n) if (rst_n) vsync =1 ' B0; 
        Reset starting from 0 else if (y_cnt==10 ' D0) vsync=1 ' B0; 




    else if (y_cnt==10 ' D2) Vsync=1 ' B1; Dividing different display interfaces wire a_dis= ((xpos>=144) && (xpos<=784)) && ((ypos>=35) && (ypos<=135)) ;//b Wire b_dis= ((xpos>=200) && (xpos<=700)) && ((ypos>=136) && (ypos<=185)); R Wire c_dis= ((xpos>=144) && (xpos<=784)) && ((ypos>=415) && (ypos<=515)); B Wire d_dis= ((xpos>=200) && (xpos<=700)) && ((ypos>=365) && (ypos<=415)); R Wire e_dis= ((xpos>=200) && (xpos<=250)) && ((ypos>=186) && (ypos<=366)); R Wire f_dis= ((xpos>=650) && (xpos<=699)) && ((ypos>=186) && (ypos<=366));
      R Wire h_dis= ((xpos>=144) && (xpos<=199)) && ((ypos>=136) && (ypos<=414));//b Wire i_dis= ((xpos>=700)&& (xpos<=784)) && ((ypos>=136) && (ypos<=414))//b always@ (Posedge clk or Negedge rst_
                       N) begin if (rst_n) begin count<=0;
                       flag1<=0;
                       flag2<=0;
                      end ELSE begin count=count+1;
                             if (count==27 ' b11110100001001000000) begin count<=0;
                                     if (flag1==9 ' D0) begin if (flag2==9 ' D0)
                                      Begin flag1=flag1+1;
                                        End ELSE begin
                           flag2=flag2-1;             End End If (flag2==9 ' D0) 
                                            Begin if (flag1==9 ' d348) begin
                                         flag2=flag2+1;
                                           End ELSE begin
                                        flag1=flag1+1;
                                       End End If (flag1==9 ' d348)
                                            Begin if (flag2==9 ' d237)
                                              Begin Flag1=flag1-1; End ELSE begin
                                               flag2=flag2+1;
                                        End End If (flag2==9 ' d237)
                                                Begin if (flag1==9 ' D0)
                                                 Begin flag2=flag2-1;
                                                   End ELSE begin
                                                    Flag1=flag1-1;
                          End End End End Wire g_dis= ((XPOS&GT;=251+FLAG1) && (XPOS&LT;=300+FLAG1)) && ((YPOS&GT;=136+FL AG2) && (YPOS&LT;=176+FLAG2));

   G RGB Pixel Point Assignment assign vga_r= valid? 
      (D_dis |b_dis|e_dis |f_dis): 1 ' b0; Assign vga_b= valid? 
    (A_dis |c_dis|h_dis |i_dis): 1 ' b0; 

Assign vga_g= valid?g_dis:1 ' B0; Endmodule

Run Result:

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