Vi. 2440 Bare Metal Development LCD operation

Six, the LCD control original address: http://blog.csdn.net/woshidahuaidan2011/article/details/51278058by jaosn Email: [Email protected]

LCD (abbreviated to LIQUID crystal display) . LCD is constructed in two parallel glass substrates placed in the LCD box, the lower substrate glass set TFT(thin film transistor), on the substrate glass set color filter, through the TFT The signal and the voltage change to control the direction of the liquid crystal molecules, so as to control the polarization of each pixel to shoot or not to achieve the display purpose. Now LCD has replaced the CRT into the mainstream, the price has fallen a lot, and has been fully popularized .

S3C2440 Displays the image through the LCD, and within 2440, there is an LCD control-related register with the following structure:

Among them, Reabank is a register group mainly contains 17 sets of parameters of the Register and the 256x16 Palette memory, the role of each register will be expanded below, LCDCDMA is for the LCD dedicated DMA channel, used to obtain the image data on the bus The Timegen and LPC3600 are used to generate LCD control timings, VIDRCS, to transmit DMA-acquired data to the LCD in a set format. LPC3600 and LCC3600 for Samsung's LCD, if not using Samsung's production of LCD, the need to prohibit LPC3600 and LCC3600.

The data sheet gives two types of LCDs, one of which is the STN (Super Twisted nematic) LCD, which is no longer described here, one is the TFT LCD which only describes the TFT LCD.

Before introducing the LCD display, first introduce several important nouns for LCD display, first look at the picture:

Figure, is a general picture of the whole picture, where the dark blue part of the actual display of the parts, the rest of the parts are non-display parts, but the non-display part of the LCD is also necessary. In the Arrows section, the LCD is displayed in order from left to right, from top to bottom. The figure HSync and VSync is a jump signal, at the end of each line, the next line at the beginning of the time, will produce a hsync signal, in a picture (frame) display, to display the next picture, will emit a vsync signal.

It is interesting to note that in addition to the dark blue part, there are other colors around it. That is, when a pixel is scanned to the far right of each line of dark blue (which can be displayed to the user), it is also necessary to scan several useless pixels to jump to the next line and emit a hsync signal (the purple part of the right side of the useless point), at which point, after the hsync signal is emitted, You still need to scan a few useless points (the useless point at this point is the point that is not displayed, the so-called useless point refers to the purple part of the left) in order to scan out the point to display to the user.

From a longitudinal perspective. When the pixel is scanned to the right end of the image to display the time, that is, the corresponding point A, the scan point does not immediately turn to the upper left to display the next frame, but still have to constantly scan a few useless lines and then jump and emit a vsync signal (at this point is the picture of the yellow part), after the vsync signal, You still need to sweep a few rows of useless pixels (the red part of the map) to display the image you want to display.

All of these pixels to be scanned are called a frame, that is, all the pixels in the graph are called a frame (useful useless points are counted), so the frequency of the vsync signal is called the vertical frequency represents the number of images that can be displayed per second. The simple explanation is that each appearance of a vsync proves that a picture is displayed. The corresponding HSync is called the horizontal frequency. The simple explanation is that each time a hsync signal appears, a scan of the complete line is proved.

The dark blue part of the figure, which is the number of rows of valid data, is called resolution.

Basic noun, and the basic display principle of LCD has been introduced, and then to control the LCD to show what you want to display, first of all to control the need to have a time series diagram, the next look at the LCD Controller timing diagram:

First of all, it can be seen that a period of vsync is a period of one frame, vsync high-level time (pulse width) is vspw+1 hsync signal period; The vbpd+1 part of the sequence diagram corresponds to the red portion of the above figure. Next is the number of rows that are effectively displayed lineval+1 a valid number of rows (corresponding to the number of lines in the Blue section), and the next frame is displayed after the time vfpd+1 the HSync cycle is required, where the vfpd+1 HSync cycle time is the yellow part of the corresponding graph. In general, a frame (the time to display a picture) is (vspw+1) + (vbpd+1) + (lineval+1) + (vfpd+1) a hsync cycle.

Then a hsync cycle is amplified in the time series diagram, the HSync high-level duration (pulse width) is hspw+1 vclk period, and the next hbpd+1 cycle is required to display the valid data, when VCLK The time of the 1 vclk cycles is the purple portion of the left side of the corresponding middle, and then the active data section is displayed, which requires a total of hozval+1 vclk cycles (the number of columns in the blue section here), and then the time needed to hfpd+1 VCLK cycle to continue showing the next line. The time hfpd+1 a vclk cycle is the purple part of the right side of the map. The time required to scan a line here is (hspw+1) + (hbpd+1) + (hozval+1) + (hfpd+1) VCLK cycles.

In order to determine the specific values of VSPW vbpd lineval vfpd hspw hbpd hozval HFPD, it is necessary to compare the results according to the LCD chip manual. To compare the data sheet of the LCD chip, there are two kinds of units in the figure, where H stands for HSync, where the CLK is the clock period of the pixel.

Compare the above figure to know vspw=9 vbpd=1 lineval=271 vfpd=1 hspw=40 hbpd=1 hozval=479 hfpd=1

Through the above two paragraphs of analysis, you can see:

A frame period (also shows the time of a picture) is (vspw+1) + (vbpd+1) + (lineval+1) + (vfpd+1) a hsync cycle,

One HSync cycle for (hspw+1) + (hbpd+1) + (hozval+1) + (hfpd+1) VCLK cycles

Therefore, a frame period = {(vspw+1) + (vbpd+1) + (lineval+1) + (vfpd+1)} * {(hspw+1) + (hbpd+1) + (hozval+1) + (hfpd+1)} VCLK Cycles

The data sheet here shows:

VCLK frequency (Hz) =vclk (Hz) = HCLK/[(clkval+1) * 2]

Where the minimum value of Clkval is 0.

So the frequency of a frame is:

Frame rate = 1/[{(vspw+1) + (vbpd+1) + (Liineval + 1) + (vfpd+1)} * {(hspw+1) + (hbpd +1) + (hfpd+1) + (hozval + 1)} *{2 x (clkval+1)/(HCLK)}]

Therefore, it is necessary to set the variable value of the formula above and give the address of the frame memory to display the data.

The next thing to say is how to store it, and before you say it, you need to know a concept BPP:

BPP (pixel depth): The pixel depth is the number of bits used to store each pixel, and it is also used to measure the resolution of the image. The pixel depth determines the number of possible colors per pixel of a color image, or determines the possible grayscale levels for each pixel of a grayscale image.

For example, each pixel of a color image is represented by a r,g,b three component, and if each component is 8 bits, then a pixel is shared with 24 bits, which means that the pixel depth is 24, and each pixel can be one of 16 777 216 (2 24) colors. In this sense, the pixel depth is often said to be the depth of the image. The more bits of a pixel, the more colors it can express, and the deeper it will be.

2440 Data Sheet has 2BPP, 4BPP, 8BPP, 16BPP, 24BPP, here only the rest of the 16BPP is similar.

If the LCD uses, 16BPP to show, 2440 is used in the way is 4 bytes to store two pixels of the BPP, which gives a pixel of the bpp to occupy 2 bytes, but there are two ways to store:

When bswp = 0, hwswp = 0 o'clock, 2440 uses the above storage mode, when BSWP = 0, Hwswp = 2440 is the following storage method:

In the LCD, the pixel points P1, P2, P3, etc. are arranged in the following way:

Using 16BPP storage, that is, red, green, and blue RGP a 16 bit, their distribution method has two kinds of 5:6:5 and 5:5:5:1, for the second way, the last intensity bit, can be regarded as GRB each has the lowest bit of color, like in the following table, VD 18 bits, 10 bits, 2 bits each, so 5:5:5:1 and R (5+1): G (5+1): B (4+1) is the same (but not understood as 2^18 color values).

The 24-bit data cable used by the LCD to transmit data, the two ways in the 24-bit transfer process are:

For other formats of BPP can refer to the data sheet, next to the palette, the color palette is a piece of 256*16 memory, when using 8BPP mode, you can find the color palette by index value, the palette is similar to 16BPP can use 5:6:5 and 5:5:5:1 two modes , and its storage format is as follows:

As you can see, the color palette has a depth of 0 to 0Xff and a width of 16bit, as you can see from the graph that the starting address of the palette is 0x4d000400 and the end address is 0X4D0007FC, where the palette uses only 32 of the low 16 bits of memory Data[31:1 6] data is invalid. If the 5:5:5:1 format is stored, the transmitted VD1 8, VD1 0, and VD2 are all transmitted in the same value data (L).

The following is the beginning of the control LCD register:

First look at the LCDCON1, functions such as:

The ENVID:LCD output signal control bit is 1 to enable

Bppmode: Selection of the corresponding BPP for the screen type

Pnrmode: Selection of screen type

Mmode: Setting the VM reversal frequency for STN LCD

Clkval: Setting the pixel clock

For tft:vclk=hclk/((clkval+1) * *)

Hclk=100mhz case, the LCD manual illustrates that VCLK is typically 9mhz,clkval=4 or 5

LINECNT: Read-only bit, minus 1 for each row of linecnt, until it is reduced to 0

Lcdcon2,lcdcon3,lcdcon4 its specific meaning in the previous analysis, no longer repeat, register functions such as:

The LCDCON5 register consists primarily of a read-only register containing some states and a polarity setting for some signals:

HWSWP: Half-word switching enable bit

BSWP: The word Exchange is the Enable bit

(The above two registers are used to set the storage arrangement of pixels in memory.)

Enlend:lend Enable Register

Pwren:lcd_pwren Enable Register

Invlend:lend the polarity of the signal, whether reverse

Invwren:pwren Signal Polarity reversal

Invven:vden the polarity of the signal, whether reverse

Invvd:vd whether the polarity of data transmission is reversed

Whether the polarity of the invvframe:vfine/hsync signal is reversed

Whether the polarity of the invvline:vline/hsync signal is reversed

INVVCLK: Set to 0 read data on VCLK falling edge, set to 10 read data on VCLK rising edge

FRM565: When 16BPP is set, is 565 or 5551

BPP24BL:24BPP mode, is low-byte data valid or high-byte data valid

Hstatus/vstatus: A read-only register that is used to obtain what part of the current pixel is scanned.

LCDCON1 to LCDCON5 Register, these 5 registers are mainly set up with the hardware closely related parameters, the next is about the frame memory register, the introduction before you need to understand some concepts, in the LCD display of the picture, you can see the real display of valid data around there are many useless data, All of these data (valid data + invalid data) is called a frame, and the real valid data is called View PORT, and its graph can be expressed as:

As can be seen from the figure, the size of the view port is the actual LCD screen size, a frame contains the view port, and the view port in a frame is movable, its position is Lcdbaseu, Lcdbasel (view PageWidth (the width of the view port, which is the width of the LCD), is determined by the start address of the port up and down two points. These values can be specified in the following registers.

The first is the LCDSADDR1 register:

Lcdbaseu: For the TFT LCD, the starting address of the memory that is used to hold the viewport (view port) (the address of the first value of view port is the location address of the upper-left corner of view port in the map), which is the start address of the frame buffer. (You can refer to the above displacement map to understand). It holds the 21st to 1th bit of the first address of the frame memory (numeric value of 32 bits).

Lcdbank: Saves the starting address of the frame memory (30th to 22nd bit of the first address of the frame memory (32 digits), and must be 4m aligned in order to move the View port window without affecting the Lcdbank value.

In general Lcdbaseu is the "21:1" bit of the frame memory start address, and Lcdbank holds the "30:22" bit of the frame memory start address.

Next LCDSADDR2:

Lcdbasel: The specific meaning can be seen above the view port of the movement of the figure understanding, for the TFT LCD, the last line of view port to save the start address, the formula is:

Lcdbasel = ((The frame end address) >>1) +1
= Lcdbaseu + (pagewidth+offsize) x (lineval+1)

The above formula through the above displacement map should not be difficult to understand, just to note that the offsize is the view port bitmap on the left and right of the two labeled Offsize and. In general, Lcdbasel storage is the size of the buffer "21:1" (Maximum frame memory is 4m, that is, the maximum is 22 bits) + offset address (the first address of frame memory).

Next is

Pagewidth:view port width, in half word (32 bit CPU half word is 16bit)

Offsize: Represents half of the last data in the previous row and the address difference between the first data in the next row, in half words. If the Offsize value 2 represents a difference of 4 half words.

Once you've set up and finished, take a look at the information settings for the palette:

Tpalval: The value of the GPG of this palette

Tpal the Enable bit of the palette.

Set the front of these registers LCD can work stably, but LCD controller in order to more likely save time, meet different needs, its arch of an LCD interrupt operation, specific look at the following several registers:

LCDINTPND interrupt suspend register, mainly indicates the LCD interrupt hangs the situation

INT_FICNT: The interrupt suspend bit, which is 0 indicates that no interrupt request has occurred, when the bit is 1 indicates that the LCD FIFO has reached the specified threshold value.

Int_frsyn: Frame synchronization interrupts the suspend bit, which is 0 for no frame synchronization interrupt request, and the bit is 1 to indicate that the frame is making an interrupt request (the LCD has finished displaying a frame).

Another register that is identical to the interrupt suspend register LCDINTPND is that the interrupt source hangs the register, they have the same function, here to explain the source of the interruption, we all know that the interruption refers to the occurrence of an event (hardware or software), the computer suspends the execution of the current program, in turn to execute another program, To handle the events that occurred, and then return to the original program to continue the operation process. Interrupts are a description of a processor's working state. We refer to the cause of the interruption or the source of the interrupt request signal as the source of the interrupt.

The corresponding interrupt source suspend register is the interrupt source suspend register, which indicates that the interrupt source hangs state

INT_FICNT: The interrupt suspend bit, which is 0 indicates that no interrupt request has occurred, when the bit is 1 indicates that the LCD FIFO has reached the specified threshold value.

Int_frsyn: Frame synchronization interrupts the suspend bit, which is 0 for no frame synchronization interrupt request, and the bit is 1 to indicate that the frame is making an interrupt request (the LCD has finished displaying a frame).

Since the LCD has these two status registers in front then there must be a corresponding interrupt screen register to mask the interruption of the occurrence, where the register is LCDINTMSK, the interrupt screen register can decide to block the interrupt source (the blocked interrupt source will not take effect).

INT_FICNT: Shielded LCD FIFO interrupt bit, which is set to 0 indicates the interrupt of the corresponding LCD FIFO, the bit set to 1 indicates the interrupt of the blocked LCD FIFO.

Int_frsyn: Shielded LCD frame sync interrupt bit, which refers to 1 to indicate a shielded frame synchronization interrupt.

Fiwsel: Determines the threshold for the FIFO of the LCD, set to 0 threshold of 4 words, set to 1 to indicate a depth of 8 words

In addition, Samsung has added a register Tconsel to control the lpc3600/lcc3600 mode for the LCD of its own production:

For this register is not introduced, the use of non-LPC3600 LCC3600 to the register "0 1" Write 0 prohibit the module can be.

All of the registers for the TFT LCD have been outlined, followed by the steps to control the LCD:

Summarize:

1, the initialization of the connection to the LCD pin, the connection way to see the Development Board schematic diagram

2, LCDCON1 to LCDCON5 used to select the type of LCD, set some hardware information.

3, CDSADDR1 to LCDSADDR3 set the address of the frame memory

4, Tpal settings, whether to use the color palette and set the data palette.

5, according to whether the use of Samsung's lpc3600 and lcc3600 LCD, if not used, it is necessary to prohibit the corresponding module

Can be set by Tconsel.

6, set whether to use interrupts, can be set by Lcdintmsk

7, control the LCD open or close.

The setup code is given below:

Voidlcd_init (void)

{

#define VBPD (1)//back shoulder with vertical sync signal

#define VFPD (1)//front shoulder with vertical sync signal

#define VSPW (9)//pulse width of vertical sync signal

#define HBPD (1)//back shoulder with horizontal sync signal

#define HFPD (1)//front shoulder with horizontal sync signal

#define HSPW (40)//pulse width of the horizontal sync signal

1, the initialization of the connection to the LCD pin, the connection way to see the Development Board schematic diagram

Rgpcup = 0xFFFFFFFF; prohibit internal pull-up

Rgpccon = 0xaaaaaaaa; GPIO pins for vd[7:0],lcdvf[2:0],vm,vframe,vline,vclk,lend

rgpdup = 0xFFFFFFFF; prohibit internal pull-up

Rgpdcon = 0xaaaaaaaa; GPIO pins for Vd[23:8]

Rgpbcon &= ~ (3<<0); LCD Backlight control pin

Rgpbcon |= (1<<0);

Rgpbdat &= ~ (1<<0); turn off the backlight light

2. LCDCON1 to the LCDCON5 used to select LCD of the type, set some hardware information.

Set pixel clock frequency, screen model, BPP mode

RLCDCON1 = (5<< 8) | (3 <<5) | (12<< 1);

RLCDCON2 = (vbpd << 24) | (271<< 14) | (VFPD << 6) | (VSPW);

RLCDCON3 = (hbpd << 19) | (479<< 8) | (HFPD);

RLCDCON4 = (HSPW);

Settings for signal polarity data storage format, etc.

RLCDCON5 = (1 << 11) | (1 <<10) | (1 << 9) | (1 << 8) | (1);

Select 565 format rising edge latch data vline/hsync vfiame/vsync Reverse storage format P1 P2

3. CDSADDR1 to the LCDSADDR3 set the address of the frame memory

 // Here's Lcdbank defined as volatile unsigned shortlcdbank[272][480];// Request Frame Memory Lcdbank is randomly assigned by the system.

rLCDSADDR1 = (((unsigned int) Lcdbank >>) << 21) | ((((unsignedint) Lcdbank) >> 1) & 0X1FFFFF);

//((unsigned int) Lcdbank >>) <<) The memory address of the A to the - the bits that are stored in the Register + to the in in bits

//(unsigned int) lcdbank) & 0x1fffff remove low bit

//(((unsigned int) lcdbank) &>> 1) 0x1fffff Memory Header Address ( + number of bits). 21~1 bits are placed in the Register 20~0

RLCDSADDR2 = (((unsigned int) Lcdbank + ((480* 272)) >> 1) &0x1fffff;

//((The frame end address) >>1) +1 The reason is (480 * 272) multiplied by 2 is because 16BPP if 8BPP then multiply 1

       // Move left First 1 bit after lower + bit

RLCDSADDR3 = (0 << 11) | (480/1);

//offsize to be 0 16BPP exactly one pixel occupies a half word

4 , Tpal set, whether to use the color palette and set the data for the palette

    /// Disable temporary palette registers

Rtpal = 0;

5 based on whether or not they use the Samsung Company's lpc3600 and the LCC3600LCD , it is necessary to prohibit the corresponding module if not used.

can be done by Tconsel to set.

// prohibited lpc3600/lcc3600 Mode

Rtconsel &= ~ ((1 << 0) | (1 <<1) | (1 << 2)) ;

6 , sets whether to use interrupts, which can be Lcdintmsk to set

Rlcdintmsk |= (3); //mask LCD Sub Interrupt

7 , Control LCD to open or close

rLCDCON1 |= 1;// to enable LCD Transmission of data signals

Lcd_power_control (1);// to enable LCD

}

Vi. 2440 Bare Metal Development LCD operation