What does high-level low mean?

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What does high-level low mean?

To understand the logic level, you must first understand the meanings of the following concepts:
1: Input high level (VIH): ensure that the input of the logic gate is the minimum input high level allowed by high voltage. When the input level is higher than VIH, it is considered that the input level is high.
2: input low level (devil): ensure that the input of the logic gate is the maximum input low level allowed by low power. When the input level is lower than devil, it is considered that the input level is low.
3: output high level (voh): ensure that the output of the logic gate is the minimum value of the output level of the high current. The output value of the logic gate must be greater than that of the voh.
4: output low level (VOL): ensure that the output of the logic gate is the maximum value of the output level at low power levels. The output value of the logic gate must be smaller than that of the vol at low power levels.
5: threshold level (VT): Each digital circuit chip has a threshold level, that is, the level when the circuit is barely able to flip. It is a voltage value between windows and VIH. For the CMOS circuit's threshold level, it is basically a 1/2 power supply voltage value, but it must ensure stable output, you must enter a high level> VIH and a low level <devil. If the input level is up or down the threshold ~ In the VIH area, the output of the circuit is unstable.
For general logic levels, the relationship between the above parameters is as follows:
Voh> VIH> VT> Devil> vol.
6: ioh: The logic gate outputs the load current (for pulling current) for high-power periods ).
7: fib: The logic gate output is the load current at low power usage (for irrigation current ).
8: iih: the input of the logic gate is the current of the high current (for the filling current ).
9: IIl: the input of the logic gate is the current at low power consumption (for pulling current ).
The door circuit output pole is directly output as the output end without load resistance in the Integration Unit. This form of door is called an open door. Open-source TTL, CMOS, and ECL are called Open-collector (OC), open-drain (OD), and open-source (OE) respectively ), when used, check whether the Pulling Resistance (OC, OD gate) or drop-down resistance (OE gate) is connected and whether the resistance is suitable. For open collector (OC) doors, the uplink resistance RL must meet the following conditions:
(1): RL <(VCC-voh)/(n * ioh + M * iih)
(2): RL> (VCC-Vol)/(OLS + M * IIl)
N: number of open doors and wires; M: Number of input ports driven.
: Common logic levels
· Logic level: TTL, CMOS, lvttl, ECL, PECL, GTL, RS232, rs422, and LVDS.
· The logical levels of TTL and CMOS can be divided into four types by typical voltages: 5 V series (5 v ttl and 5 v cmos), 3.3v series, 2.5v series, and 1.8v series.
· 5 v ttl and 5 v cmos logical levels are common logical levels.
· 3. logical levels of 3 V and below are called low-voltage logical levels, which are commonly used as lvttl levels.
· The logical levels of low voltage include 2.5v and 1.8v.
· ECL/PECL and LVDS are differential input and output.
· RS-422/485 and RS-232 are serial port interface standard, RS-422/485 is differential input output, RS-232 is single-ended input output.