What DSP should know best

How does one mix 1.5 V/3.3v?
The development of TI DSPs is the same as that of Integrated Circuits. The new DSPs are all 3.3v, but many peripheral circuits are still 5 V. Therefore, in the DSP system, there are often 5 V and 3 v dsp mixed connection problems. In these systems, Note: 1) the DSP outputs to a 5 V circuit (such as D/A), which can be directly connected without any buffer circuit. 2) DSP input 5 V signal (such as A/D), because the input signal voltage is greater than 4 V, exceeds the DSP power supply voltage, the DSP's external signal has no protection circuit, buffer is required, such as 74lvc245, to convert a 5 V signal into a 3 V signal. 3) The JTAG port signal of the simulator must also be 3.3 V; otherwise, the DSP may be damaged.

2. Why is the on-chip ram dsp highly efficient?
At present, DSP is developing more and more on-chip Memory RAM. to design an efficient DSP system, you should select a DSP with a larger on-chip RAM. Compared with external memory, in-chip RAM has the following advantages: 1) the speed of In-chip RAM is faster, and the DSP does not have to wait for operation. 2) For the c2000/c3x/C5000 series, some in-chip memory can be accessed twice in one instruction cycle, making the instruction more efficient. 3) The on-chip RAM runs stably and is not affected by external interference or external interference. 4) Multi-bus in DSP chip. when accessing the on-chip RAM, access to other bus is not affected and the efficiency is high.

3. Why did DSP grow from 5 V to 3.3 V?
The development of ultra-large scale integrated circuits has grown from 1um to 0.1um. The power supply voltage of the chip has also decreased, and the power consumption has also decreased. DSP also grew from 5 V to 3.3 V, and core voltage to 1 v. At present, the peripherals of mainstream DSPs have developed to be 3.3 V. The prices and power consumption of 5 V DSPs are both prices, and they are gradually replaced by DSP 3.3v.

4. How do I select a DSP power supply chip?
Tms320lf24xx: tps7333qd. The value ranges from 5 V to 3.3 V, and the maximum value is 500mA.
TMS320VC33: tps73hd318pwp, 5 V changed to 3.3v and 1.8 V, up to 750mA.
Tms320vc54xx: tps73hd318pwp, 5 V changed to 3.3v and 1.8 V, Max 750mA; tps73hd301pwp, 5 V changed to 3.3v and adjustable, Max 750mA.
Tms320vc55xx: tps73hd301pwp, 5 V changed to 3.3v and adjustable, Max. 750mA.
TMS320C6000: pt6931, tps56000, maximum 3A.

5. How can I use the software?
The DSP has a fast instruction cycle. when accessing slow memory or peripherals, you need to wait. The waiting time is divided into hardware waiting and software waiting. The waiting time of each series is different.
1) For the c2000 series: The Hardware Wait signal is ready, which is usually not waiting. The software wait is determined by the wsgr register. A maximum of seven waits can be added. The program memory, data storage, and I/O can be set separately.
2) For the c3x series: The Hardware Wait signal is/rdy, and the low level is not waiting. The software wait is determined by the sww and wtcny in the bus control register. A maximum of seven waits can be added, but the wait is not segmented, and the entire space is valid except in-chip.
3) for the C5000 series: The Hardware Wait signal is ready, which is usually not waiting. The software wait is determined by the swwcr and swwsr registers. up to 14 waits can be added. Program memory, control program memory, data storage, and I/O can be set separately.
4) for the C6000 series (only for non-synchronous memory or peripherals): The hardware waits for the signal to be Ardy, not waiting for high power. The software wait is determined by the external memory interface control register. The timing of bus access to the external memory or device can be set to facilitate the same asynchronous memory or peripheral interface.

6. Why should we relocate the interrupt vectors?
To facilitate DSP Memory configuration, DSP interrupt vectors can be located again, that is, registers can be placed anywhere in the memory space. Note: c2000 interrupt vectors cannot be relocated.

7. Can the highest frequency of DSP be obtained from the chip model?
The highest frequency of ti dsp can be obtained from the chip model, but each series is not necessarily the same.
1) tms320c2000 series:
TMS320F206-the maximum clock speed is 20 MHz.
TMS320C203/c206-the maximum clock speed is 40 MHz.
Tms320f24x-the maximum clock speed is 20 MHz.
Tms320lf24xx-the maximum clock speed is 30 MHz.
Tms320lf24xxa-the maximum clock speed is 40 MHz.
Tms320lf28xx-the maximum clock speed is 150 MHz.
2) tms320c3x series:
TMS320C30: The maximum clock speed is 25 MHz.
Tms320c31pql80: The maximum clock speed is 40 MHz.
Tms320c32pcm60: The maximum clock speed is 30 MHz.
Tms320vc33pg150: The maximum clock speed is 75 MHz.
3) tms320c5000 series:
Tms320vc54xx: The maximum clock speed is 160 MHz.
Tms320vc55xx: The maximum clock speed is 300 MHz.
4) TMS320C6000 series:
TMS320C62XX: The maximum clock speed is 300 MHz.
Tms320c67xx: The maximum clock speed is 230 MHz.
TMS320C64xx: The maximum clock speed is 720 MHz.

8. Can the DSP be used for frequency reduction?
Yes, the DSP clock speed has a certain range of work, So DSP can be used for lower frequency.

9. How do I select an external clock?
The internal instruction cycle of the DSP is high, and the clock speed of the external crystal oscillator is not enough. Therefore, most of the DSPs have PLL. But each series is different.
1) tms320c2000 series:
Tms320c20x: the PLL can be 2, x 1, x 2, and x 4, so the external clock can be 5 MHz-40 MHz.
TMS320F240: PLL can be 2, × 1, × 1. 5, × 2, × 2. 5, X 3, x 4, x 4. 5, X 5 and x 9, so the external clock can be 2.22 MHz-40 MHz.
Tms320f241/c242/f243: the PLL can be × 4, so the external clock is 5 MHz. Tms320lf24xx: the PLL can be adjusted by RC, so the external clock is 4 MHz-20 MHz.
Tms320lf24xxa: the PLL can be adjusted by RC, so the external clock is 4 MHz-20 MHz.
2) tms320c3x series:
Tms320c3x: No PLL, so the external clock speed is twice the operating frequency.
TMS320VC33: the PLL can be 2, × 1, × 5, so the external clock speed can be 12 MHz-100 MHz.
3) tms320c5000 series:
Tms320vc54xx: the PLL can be listen 4, listen 2, × 1-32, so the external clock speed can be 0.625 MHz-50 MHz.
Tms320vc55xx: the PLL can be listen 4, listen 2, × 1-32, so the external clock speed can be 6.25 MHz-300 MHz.
4) TMS320C6000 series:
TMS320C62XX: the PLL can be 1, x 4, X 6, X 7, x 8, x 9, x 10, and x 11. Therefore, the external clock speed can be 11.8 MHz-300 MHz.
Tms320c67xx: the PLL can be 1 or 4, so the external clock speed can be 12.5 MHz-230 MHz.
TMS320C64xx: the PLL can be 1, 6, or 12, so the external clock speed can be 30 MHz-720 MHz.

13. How do I select the DSP's external memory?
The DSP speed is fast. To ensure the running speed of DSP, the external memory needs to have a certain speed. Otherwise, the DSP needs to add a waiting period when accessing the external memory.
1) For the c2000 series: The c2000 series can only be directly connected with asynchronous memory. The current maximum speed of c2000 series DSPs is 150 MHz. We recommend that you use the following memory:
CY7C199-15: 32 K × 8, 15ns, 5 V;
CY7C1021-12: 64k x 16, 15ns, 5 V; CY7C1021V33-12: 64k x 16, 15ns, 3.3 V.
2) For c3x series: The c3x series can only be directly connected to asynchronous memory. The maximum speed of the c3x series DSP is 40 MHz for 5 V and 75 MHz for 3.3v. To ensure that the DSP is not waiting for operation, the external memory speed is required <25ns and <12ns respectively. We recommend that you use the following memory:
ROM: AM29F400-70: 256k x 16, 70ns, 5 V, add a wait;
AM29LV400-55 (sst39vf400): 256k x 16, 55ns, 3.3 V, add two waits (no faster flash at present ).
SRAM: CY7C199-15: 32 k x 8, 15ns, 5 V;
CY7C1021-15: 64 k x 16, 15ns, 5 V;
CY7C1009-15: 128k x 8, 15ns, 5 V;
CY7C1049-15: 512k x 8, 15ns, 5 V;
CY7C1021V33-15: 64 K × 16, 15ns, 3.3 V;
CY7C1009V33-15: 3.3 k x 8, 15ns, V;
CY7C1041V33-15: 256k x 16, 15ns, 3.3 V.
3) for the C54X series: The C54X series can only be directly connected to asynchronous memory. The speed of the C54X series DSPs is 160 MHz or MHz. To ensure that the DSPs are not waiting for operation, the external memory speed is <10ns or <6ns. We recommend that you use the following memory:
ROM: AM29LV400-55 (sst39vf400): 256k × 16, 55ns, 3.3 V, add 5 or 9 waits (no faster flash at present ).
SRAM: CY7C1021V33-12: 64 k x 16, 12ns, 3.3 V, add a wait;
CY7C1009V33-12: 3.3 k x 8, 12ns, V, add a wait.
4) for c55x and C6000 series: Only c55x and C6000 in ti dsp can be connected to the synchronous memory, and the synchronous memory can ensure higher system data exchange efficiency.
ROM: AM29LV400-55 (sst39vf400): 256k × 16, 55ns, 3.3 V.
SDRAM: HY57V651620BTC-10S: 64 m, 10ns.
Sbsram: CY7C1329-133AC, 64 K × 32;
CY7C1339-133AC, k x 32.
FIFO: CY7C42x5V-10ASC, 32 K/64 k x 18.

14. how powerful is the DSP chip?
The DSP has strong driving capabilities and can be connected to more than 8 standard TTL doors without driving.

15. Are you sure you want to debug the tms320c2000 series Frequently Asked Questions?
1) A single step can be run. During continuous running, the total return address is 0. If watchdog is not involved, the reset DSP continuously returns to the 0 address.
2) The out file cannot be loaded into the flash in the chip: Flash is not Ram and cannot be written using simple write commands. It must be written by a special program. The load command in CCS and C source debugger cannot be written to flash. The out file can only be loaded to on-chip RAM or off-chip RAM.
3) how to add breakpoints to flash: You can use one-step debugging or hardware breakpoint to add breakpoints to flash. Software breakpoints cannot be added to Rom. Hardware breakpoint, set the address of the storage, and interrupt when accessing this address.
4) interrupt vector: the interrupt vector of c2000 cannot be relocated. Therefore, the interrupt vector must be placed in the flash at the beginning of 0. When debugging the system, the code is placed in Ram, And the interrupt vector must also be placed in flash.

16. How do I debug the tms320c3x series Frequently Asked Questions?
1) memory configuration of TMS320C32: The program memory of TMS320C32 can be configured as 16-bit or 32-bit, and the data memory can be configured as 8-bit, 16-bit, or 32-bit.
2) PLL control of TMS320VC33: the PLL control end of TMS320VC33 can only be connected to 1.8 V, not 3.3v or 5 V.

17. How to debug multiple DSPs?
For DSP with mpsd simulation port (TMS320C30/C31/c32), one of the DSP can only be debugged at a time, instead of one set of simulators. For DSP with JTAG simulation port, you can concatenate JTAG and debug multiple DSPs simultaneously using a set of simulators. Each DSPs can be debugged in different windows with different names. Note: If you add a driver between the JTAG and DSP, you must use a Fast door circuit. You cannot use a slow door circuit such as LS.

18. Why is CPLD used in the DSP system?
The speed of DSP is fast, and the decoding speed must be fast. The small-scale logic device decoding method cannot meet the requirements of the DSP system. At the same time, the DSP system also often needs the cooperation of external fast components. These components are usually specialized circuits and can be implemented by Programmable devices. The CPLD has strict timing, fast speed, and good programmability. It is very suitable for decoding and specialized circuits.

19. What are common chips used by DSP Systems?
1) Power Supply: tps73hd3xx, tps7333, tps56100, pt64xx...
2) Flash: am29f400, am29lv400, sst39vf400...
3) SRAM: cy7c1021, cy7c1009, cy7c1049...
4) fif cy7c425, cy7c42x5...
5) dual port: cy7c136, cy7c1342, cy7c1342...
6) sbsram: cy7c1329, cy7c1339...
7) SDRAM: hy57v651620btc...
8) CPLD: cy37000 series, cy38000 series, cy39000 series...
9) PCI: pci2040, cy7c09449...
10) USB: an21xx, cy7c68xxx...
11) CODEC: tlv320aic23, tlv320aic10...
12) A/D, D/A: ads7805, tlv2543...
For more information, see www.ti.com and www.cypress.com.

20. What is boot loader?
The speed of DSP is as fast as possible, the speed of EPROM or flash is slow, and the ram in DSP is fast, and the off-chip RAM is also fast. In order for the DSP to make full use of its capabilities, the program code must be run in Ram. To facilitate code migration from Rom to ram, Ti fixed a program at the factory in DSP without flash, after power-on, code is moved from Rom or peripherals to the ram specified by the user. This program is called "Boot Loader ".