wince6.0+i.mx515 the hard reset system has no sound problems after suspension

wince6.0+i.mx515 the hard reset system has no sound problems after suspension

After the device hangs, the hard reset starts and the system has no sound. After the hardware engineer confirms that the VDDD and Vdda power to the audio module SGTL5000 have been suspended, the hard reset boot process is either low-level. Let's look at the power supply for this two pin.

Figure 1

1v2_dig2 and 1v65 are powered by the VGEN1 and Vdig of the Pmic (MC13892) respectively.

Figure 2

The voltage range of the audio chip vddd is 1.1~2.0v,vdda voltage range is 1.62~3.6v.

It is confirmed that the eboot inside the Pmic initialization code does not do the relevant settings, the following is based on the relevant parts of the pmic to write code, but first look at the data pmic related instructions.

1. VGEN1 section

Output of general purpose 1 regulator.

Figure 3

Since the voltage range of the audio chip vddd is 1.1~2.0v, the hardware setting is identified as 1V2_DIG2, so here we choose to output 1.20V. This corresponds to the following register control.

Figure 4

The VGEN10 and VGEN11 of register 30 need to be set, the corresponding code

     Vgen = 1v2_dig2 = 1.2 (Power audio) if (! Oalpmicwritemasked (mc13892_reg_set0_addr,                           csp_bitfmask (mc13892_reg_set0_vgen1),                           csp_bitfval (MC13892_ REG_SET0_VGEN1, 0)))    {       oalmsg (Oal_error, (_t ("Oalpmicinit:unable to Configure vgen1\r\n"));       Goto cleanUp;           }

Figure 5

The Vgen1en bit of register 32 needs to be enabled, the corresponding code is as follows:

VGEN1 Enable        if (! Oalpmicwritemasked (mc13892_reg_mod0_addr,                           csp_bitfmask (mc13892_reg_mode0_vgen1en),                            CSP_BITFVAL (MC13892 _reg_mode0_vgen1en,enable))    {       oalmsg (Oal_error, (_t ("oalpmicinit:unable to Enablevgen1\r\n")));       Goto cleanUp;           }

2. Vdig

Output regulator Digital. Low Voltagedigital (DPLL, GPS).

Figure 6

The voltage range of the audio Vdda is 1.62~3.6v, the audio driver chooses 1.8V, in order to remain consistent, here also chooses 1.8V.

Figure 7

The VDIG0 and VDIG1 of register 30 need to be set, the corresponding code is as follows.

Vdig setting        if (! Oalpmicwritemasked (mc13892_reg_set0_addr,                            csp_bitfmask (mc13892_reg_set0_vdig),                           csp_bitfval (MC13892_REG _set0_vdig, 3)))///1.8v                           //csp_bitfval (Mc13892_reg_set0_vdig, 2)))///1.65v                           //csp_bitfval (mc13892_reg_set0 _vdig, 0)))///1.05v    {       oalmsg (Oal_error, (_t ("oalpmicinit:unable to configurevdig\r\n"));       Goto cleanUp;           }

Figure 8

The Vdigen of register 32 needs to be enabled, the corresponding code is as follows:

Vdig Enable         if (! Oalpmicwritemasked (mc13892_reg_mod0_addr,                           csp_bitfmask (Mc13892_reg_mode0_vdigen),                           CSP_BITFVAL (MC13892_ Reg_mode0_vdigen, ENABLE))    {       oalmsg (Oal_error, (_t ("oalpmicinit:unable to enablevdigen\r\n"));       Goto cleanUp;           }

to resolve this issue.

Copyright NOTICE: This article for Bo Master original article, without Bo Master permission not reproduced.

wince6.0+i.mx515 the hard reset system has no sound problems after suspension