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Folder 1 processors and MIPS 2 programmable logic devices and Verilog HDL 3 Openmips Processor Blueprint for teaching edition 4 The first instruction of the Ori 5 logic, SHIFT and NOP 6 Moving 7 arithmetic 8 Transfer 9 Load/store Ten co-processor One Exception A Practice Version Openmips - Small Sopc - Validation the Transplant Uc/os-ii - Appendix A tutorial Openmips Interface description of each module - Appendix B openmips Implementation of all instructions and corresponding machine code - References

processors and MIPS

1. Basic isa:x86 ARM SPARC Power MIPS

programmable logic devices and Verilog HDL

1. Different Pld:pla PAL GAL PROM EPLD CPLD FPGA
   1. Product-based: With or gate + storage element (trigger)
   2. Lookup table-based: FPGA general input variable <=5
2. Schematic diagram (Schematic)
3. Verilog HDL
   1. Module
   2. Port:input, output
   3. Data type:
      1. NET type:wire (0 1 X Z) Tri wor trior Wand triand tri1 tri0 supply0 supply1
      2. Type variable: Reg integer Real
   4. Logic function: Assign (clogging = non-clogging <=)
      1. Always
         1. Sensitive signal: Level/Edge (Posedge, Negedge)
      2. Initial
   5. Compiler instructions: ' Define ' include ' ifdef ...
4. Synthesis (Synthesis): Algorithmic/Behavioral Description--RTL-------------PLD grid table
5. Modelsim Simulation

Openmips Processor Blueprint for teaching edition

1. Level 5 Pipeline: Refer to, decode, run, access, write back

The first instruction of the Orilogic, SHIFT and NOP

1. Related issues (pipelining introduces concurrent competition?) Each stage can be treated as a separate HDL module)
   1. Data Related: Raw WAR WAW ==> openmips only has raw correlation, such as: Ori $, $, 0x1100; Ori, $ $, 0x0020
      1. P111 assumes that the read register is to be written on the next clock rising edge. The data that will be written directly as the result output
         1. if (Reg2_read_o==1 ' B1 && ex_wreg_i==1 ' B1 && ex_wd_i==reg2_addr_o begin reg2_o <= ex_wdata_i;
      2. Insert Pause Period
      3. Compiler scheduling (command reflow)
      4. Data pre-push

Moving

1. Special registers Hi, LO?

arithmetic

1. Pipeline pause: Keep the PC intact, at the same time before the nth stage of the pause
   1. CTRL module: There may be a pause request only in the decoding and running phase
2. Multiply add instruction: Is this a bit off the principle of RISC?
3. Division Instruction (Trial business law)

Transfer

1. Delay slots
   1. Assume the transition during the run phase. There will be 2 invalid instructions.
   2. The instruction that has entered the reference stage is still invalid: the transfer inference can be performed during the decoding phase. Avoid wasting clock cycles
2. P210 Bal is a special case of Bgezal (rs=0)

Load/store

1. p258 the relevant specifications of the Wishbone bus?
2. p268 MIPS32 Special semaphore mechanism: there is no guarantee that atomic operation must be atomic, and it is agreed that the test set is executed without atomicity. But let ' settings ' take effect only when the atom is actually executing
   1. Link Loading ll:llbit
   2. Conditional Storage SC
3. Load related issues
   1. Check to see if there is a load associated with the previous instruction during the decoding phase. Assumption exists. Let the decoding, take the finger pause, and run, access, write back continue (equivalent to inserting a NOP)

co-processor

1. The mips32:cp0 is used as a system control, CP1, and CP3 as floating-point processing. CP2 reserved
2. Registers in the CP0
   1. Status
   2. MMU Related: ENTRYLO0/1 Context
   3. TLB correlation: Index Random pagemask Wired entryhi ...
   4. Exception: Badvaddr cause EPC
   5. Timed Interrupt: Compare

Exception

1. Type: RESET, Soft Reset, DSS DINT NMI, Machine Check, Interrupt, ...
2. Exact exception (k, transactional?) ）
   1. Handle exceptions in the order in which they are run, rather than in the order in which they occur?
3. Assuming that an exception occurs in the delay slot, then the value saved to the EPC is PC-4, otherwise the PC
4. Syscall
5. Eret
6. p332 Assign excepttype_o = {B0, Excepttype_is_eret, 2 ' B0, Instvalid, Excepttype_is_syscall, 8 ' B0};

Practice Version OpenmipsSmall SopcValidationTransplant Uc/os-iiAppendix A tutorial Openmips Interface description of each moduleAppendix B openmips All instructions to implement and the corresponding machine codeReference

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