X86 register description

X86 register description
EBP and ESP are 32-bit sp, BP
ESP is a stack pointer.
EBP is the base address pointer.
The relationship between ESP and SP is like the relationship between ax and Al and AH.

32-bit CPUs contain the following registers:

Four data registers (eax, EBX, ECx, and EDX)
2 address changes and pointer registers (ESI and EDI) 2 pointer registers (ESP and EBP)
Six segment registers (ES, Cs, SS, DS, FS, and GS)
1 Instruction Pointer register (EIP) 1 flag register (eflags)

1. Data Register

Data registers are mainly used to save information such as the operands and operation results, thus saving the time required to read the operands by occupying the bus and accessing the memory.

The 32-bit CPU has four 32-bit General registers eax, EBX, ECx, and EDX. Access to low 16-bit data does not affect high 16-bit data. These
The low 16-bit registers are named ax, BX, CX, and DX respectively, which are consistent with the registers in the previous CPU.

4 16-bit registers can be divided into 8 independent 8-bit registers (ax: Ah-Al, Bx: bh-BL, CX: ch-cl, DX: DH-DL ), each mail
The memory has its own name and can be accessed independently. Programmers can flexibly process words and words by taking advantage of the "severable" feature of data registers.
Section information.

Registers ax and Al are usually called accumulator. Operations with accumulators may take less time. Accumulators can be used for multiplication,
Operations such as division and input/output are frequently used;
Register BX is called base register ). It can be used as a memory pointer;
Register CX is called count register ). It is used to control the number of loops during loop and string operations; in-place operations
When multiple digits are removed, Cl is used to specify the number of digits;
Register dx is called a data register ). During multiplication and division operations, it can be used as the default operand for calculation.
The port address that can be used to store I/O.

In a 16-bit CPU, ax, BX, CX, and DX cannot be used as the base address and address change register to store the address of the storage unit, but in a 32-bit CPU, the 32-bit
Registers eax, EBX, ECx, and EDX can not only transmit data, store temporary data to save arithmetic logic operation results, but also serve as pointer registers,
Therefore, these 32-bit registers are more universal.

2. Address Change register

The 32-bit CPU has two 32-bit General registers ESI and EDI. Its Low 16-bit value corresponds to the Si and Di in the previous CPU, and does not affect the access to low 16-bit data.
High 16-bit data.

Registers ESI, EDI, Si, and Di are called index register, which are mainly used to store the offset of the storage unit in the segment,
They can be used to address multiple storage operations and facilitate access to storage units in different addresses.

The address change register cannot be divided into eight-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations.

They can be used as general memory pointers. In the execution process of string operation commands, they have specific requirements and
Special features.

3. pointer register

The 32-bit CPU has two 32-bit General registers, EBP and ESP. Its Low 16-bit value corresponds to the same memory and SP in the previous CPU, and its access to low 16-bit data does not affect
High 16-bit data.

Registers EBP, ESP, BP, and SP are known as pointer register and are mainly used to store the offset of the storage unit in the stack,
They can be used to address multiple storage operations and facilitate access to storage units in different addresses.

Pointer registers cannot be divided into eight-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations.

They are mainly used to access the storage units in the stack and stipulate that:

BP is a base pointer register that can be used to directly access data in the stack;
SP is the stack pointer register, which can only access the top of the stack.

4. segment register

Segment registers are set based on the management mode of memory segments. The physical address of the Memory Unit is composed of the segment register value and an offset.
In this way, two smaller-digit values can be combined into a memory address that can access a large physical space.

Segment registers inside the CPU:

CS-code segment register (code segment register), whose value is the segment value of the code segment;
DS-data segment register (data segment register), whose value is the segment value of the data segment;
Es -- extra segment register; its value is the segment value of the additional data segment;
Ss -- stack segment register (stack segment register), whose value is the segment value of the stack segment;
FS -- extra segment register; its value is the segment value of the additional data segment;
GS -- extra segment register; its value is the segment value of the additional data segment.

In a 16-bit CPU system, it has only four segment registers. Therefore, the program can directly access up to four segments in use at any time.
In a microcomputer system, it has six segment registers. Therefore, programs developed in this environment can access up to six segments at the same time.

The 32-bit CPU has two different ways of working: real-time mode and protection mode. In each mode, segment registers have different functions. Simple Regulations
The ticket is described as follows:

Implementation Method: CS, DS, es, and SS of the first four segments are exactly the same as those of the previous CPU segments. The logic of the memory unit
The address is still in the format of "segment value: Offset. To access data in a memory segment, the offset between the register and the storage unit must be used.
Protection Mode: In this mode, the situation is much more complicated. The Block Value loaded into the segment register is not a segment value, but a value called "selector ..

5. Instruction Pointer register

The 32-bit CPU extends the instruction pointer to 32-bit and records it as an EIP. The 16-bit low of the EIP works the same as the IP address in the previous CPU.

The EIP and instruction pointer are the offsets of the commands to be executed next time in the code segment. In scenarios with prefetch commands
In an available system, the next command to be executed is usually prefetch to the command queue unless it is transferred. Therefore, when understanding their functions
The command queue is not considered.

In actual mode, because the maximum range of each segment is 64 K, the high 16 bits in the EIP must be 0. At this time, it is equivalent to only using its low 16 bits
To reflect the execution order of commands in the program.

6. Mark register

I. Operation Result flag
1. Carry mark CF (carry flag)
The carry mark CF is used to indicate whether the operation generates carry or borrow digits. If the highest bit of the calculation result produces a carry or borrow digit, the value is 1; otherwise, the value is 0.

This flag is used for addition and subtraction of the number of characters (in bytes), comparison of the number of unsigned values, and shift between words (in bytes, commands that specifically change the CF value.

2. Parity mark PF (parity flag)
The parity mark PF is used to reflect the parity of the number of "1" in the calculation result. If the number of "1" is an even number, the PF value is 1; otherwise, the value is 0.

PF can be used for parity check or to generate parity bits. In the process of data transmission, in order to provide the reliability of transmission, if the parity method is adopted, this flag can be used.

3. Auxiliary carry flag AF (Auxiliary carry flag)
In the following cases, the value of the secondary carry flag AF is set to 1; otherwise, the value is 0:

(1) When the word operation occurs, the lower byte is carried to the high byte or the borrow digit;
(2) When the byte operation occurs, the lower 4 bits are carried to the upper 4 bits or the borrow bits.

For the above 6 operation result flags, in general programming, flags CF, ZF, SF, and of are frequently used, the use frequency of flag pF and AF is low.

4. Zero flag (ZF)
The zero sign ZF is used to indicate whether the calculation result is 0. If the calculation result is 0, the value is 1; otherwise, the value is 0. You can use this flag when determining whether the calculation result is 0.

5. Sign SF (sign flag)
Symbol mark (SF) is the symbol bit used to reflect the calculation result. It is the same as the highest bit of the calculation result. In a microcomputer system, the signed number uses the complement representation. Therefore, SF also reflects the positive and negative signs of the calculation result. When the calculation result is a positive number, the value of SF is 0; otherwise, the value is 1.

6. Overflow flag)
Overflow sign of indicates whether the result of the addition or subtraction operation of the number of symbols overflows. If the calculation result exceeds the range expressed by the current number of BITs, it is called overflow. The value of is set to 1. Otherwise, the value of is cleared to 0.

"Overflow" and "carry" are two different meanings. Do not confuse them. For details, refer to the relevant chapter in the computer composition principles course.

Ii. Status Control flag
The status control flags are used to control CPU operations. They must use special commands to change the status control flags.

1. Tracking mark TF (trap flag)
When the trace flag TF is set to 1, the CPU enters the single-step execution mode, that is, each execution of a command generates a single-step interruption request. This method is mainly used for program debugging.

There are no special commands in the command system to change the TF value of the flag, but the programmer can use other methods to change its value.

2. If (Interrupt-enable flag)
The interrupt flag if is used to determine whether the CPU responds to the interrupt requests that can be blocked outside the CPU. However, no matter what the value of this sign is, the CPU must respond to the interrupt requests from the outside of the CPU that cannot be blocked and the interrupt requests generated inside the CPU. The specific provisions are as follows:

(1) When if = 1, the CPU can respond to the interrupt requests externally blocked by the CPU;

(2) When if = 0, the CPU does not respond to the interrupt requests that can be blocked outside the CPU.

The CPU command system also has special commands to change the if value of the flag.

3. direction sign DF (Direction Flag)
The direction sign (DF) is used to determine the direction in which the pointer register is adjusted when the serial operation command is executed. Specific provisions are provided in section 5.2.11-string operation instructions. In the microcomputer instruction system, special commands are also provided to change the value of the Flag DF.

3. 32-Bit Flag
1. iopl (I/O privilege level)
The I/O privileged flag is expressed by two binary bits, also known as an I/O privileged level field. This field specifies the privileged level required to execute the I/O command. If the current privileged level is less than or equal to the iopl value, the I/O command can be executed. Otherwise, a protection exception occurs.

2. nested task flag NT (nested task)
The nested task flag NT is used to control the iret execution of the interrupt return command. The specific provisions are as follows:

(1) When Nt = 0, use the stored values in the stack to restore eflags, Cs, and EIP, and perform regular interrupted return operations;

(2) When Nt = 1, interrupt return is realized through task conversion.

3. Restart flag)
The restart mark RF is used to control whether debugging failures are accepted. NOTE: If RF is set to 0, the debugging fault is "accepted"; otherwise, the fault is rejected. After successfully executing a command, the processor sets the RF to 0. When a non-debugging fault is received, the processor sets it to 1.

4. Virtual 8086 mode mark VM (Virtual 8086 Mode)
If the value of this flag is 1, it indicates that the processor is in the virtual 8086 mode. Otherwise, the processor is in the normal protection mode.