Zedboard How to control DDR read and write from PL end (vi)

The previous section addressed the issue of DDR addressing, such as:

From the official documentation we saw that the DDR address was started from 0008_0000, then we began to modify the IP core code that Xilinx provided us. Actually very simple, the previous section has analyzed the address to stay in the 0000_1000 reason, now we only need to put Write_burst_counter's bit width to become big.

From the table above to see the address range from full 0 to full 1, calculate the need to know the width of 27, that is C_no_bursts_req = 26;

RePack the IP core to generate the bitstream. Start debugging

Since the address from the 0003_0000 is a reserved bit, theoretically, when we write here should be error, but in fact, there is no, there are two pictures above to see that the error is from 0003_07C0, the specific reason for further digging

Similarly, the theoretically starting address should return to normal, but in fact it starts normally from 0008_07c0.0008_0000.

here, from PL to control the DDR read and write basic has been successful , but two places are 07c0, in the end why? Still need to study further, the document is all in English, looks a little hard, progress may be slow

By the To, Jeff Johnson also have a good tutorial on using AXI DMA: http://www.fpgadeveloper.com/2014/08/using-the-ax I-dma-in-vivado.html, interested can refer to

Zedboard How to control DDR read and write from PL end (vi)