ZEDBOARD--ZYNQ using its own peripheral IP to allow arm PS access to FPGA (eight) reprint

Article source http://blog.chinaaet.com/detail/34609

Familiar with XPS operation, IP Add, bus connection Setup, graphical method check (open graphical Design view), check bus and port connection.

In the icon below file, open Export to SDK and start, complete program writing.

Refer to the superb sunny blog http://www.cnblogs.com/surpassal/, using XPS to add additional IPs to the PS processing system. Add a gpio from the IP Catalog tag and connect to the 8 LEDs on the Zedboard board. When the system is established, the bitstream is generated and the peripherals are tested. There is also a very important custom user Ipcore design, next experiment to do this (initially with simple LED and SW for example). This experiment uses a self-brought peripheral IP.

The platform used is the XPS 14.2+sdk 14.2

A hardware configuration

1. Start XPS Creation project create New project Using Basesystem Builder

Create a project. Because the PS system and FPGA connections are using the Axi interface, the internal interconnect type (interconnect type) is selected as Axi.

Select the design platform for ZynqZC702

To the peripheral configuration interface, the system will default to GPIO_SW and leds_4bits these two peripherals, we do not need, remove

2. Add Axi Gpio Peripherals

Enter the main interface

After the project is established, in Ipcatalog, locate the Generalpurpose IO, locate the AXI GPIO, and double-click Add to the System.

Modifying a symbol instance an alias is called a axi_led, and this name is the component that will be instantiated to be connected to Ps. Change the length to 8, other default.

OK appears after

Click OK,

By opening the Businterfaces tab, you can see that the system summary now has PS (here is processing_systems7_0), added peripheral axi_lds, and Axi internal interconnect bus axi_interconnet_1. You can see that for axi_interconnet_1, PS is the Axi Master device and the peripherals are axi slave devices.

In the Port tab, set gpio_io in io_if to external Ports and change the port name to LED. LED is the top-level external pin name, note here and reference blog is different. Follow the references in the blog to not succeed.

0521 Note: The name here has been tried, and cannot be changed, so the UCF file has the same name.

3. Set PIN constraints

In the Project tab, locate the SYSTEM.UCF constraint file,

4, click Generate bitstream, Generate bitstream

5. Import the hardware configuration into the SDK and launch the SDK. The bitstream and BMM files need to be included in the SDK as well.

II. creation of software programs

Use the New Project Wizard. Note that the project template is used here as Memory Tests.

After the new project, there will be several storage space test files that we do not need to delete.

Modify the main file with the following content

@ Superb sunny http://www.cnblogs.com/surpassal/#include <stdio.h>

#include "Xparameters.h"

#include "Xil_types.h"

#include "Xstatus.h"

#include "xil_testmem.h"

#include "xgpio.h"

#include "platform.h"

void print (char *ptr);

int main ()

{

Static Xgpio led_ptr;//defining Gpio pointers

int xstatus;//function return status

Init_platform ();

Print ("Zedboard project_7:ps_axi_led\n\r");

Print ("Xzy September 18, 2013 18:12:31\n\r");

Pay attention to the following must change the name Oh, before xpar_axi_lds_device_id

Xstatus = Xgpio_initialize (&led_ptr,xpar_axi_led_device_id);

if (xst_success! = xstatus)

Print ("GPIO INIT failed\n\r");

Xgpio_setdatadirection (&led_ptr, 1,0x00);//channel 1; set direction 0 Output 1 input

Xgpio_discretewrite (&led_ptr, 1,0XAA);

Cleanup_platform ();

}

Before downloading the software program, you need to burn the bitstream file like an FPGA to configure the FPGA. In the toolbar, Xilinx Tools->program FPGAs can also use the device configuration->download bitstream in XPS for other ways of configuring FPGAs.

After configuring the FPGA, download the software program, you can see the HyperTerminal display debugging information:

Note: HelloWorld project is also possible, not necessarily a memory test project.

ZEDBOARD--ZYNQ using its own peripheral IP to allow arm PS access to FPGA (eight) reprint