44b0 UART enabling FIFO

At first, I thought that FIFO was too mysterious (although clearly defined, first-in-first-out buffer), and the sending buffer was the same as the first-in-first-out buffer. The sending buffer is 16 bits, and the low 8 bits are the data zone, while the FIFO unit is measured in bytes (actually a character, because each frame number has a start bit and a stop bit ). I am confused. How does it work? I am really limited in ability. I can understand it only one afternoon. What is the use of the first-in-first-out buffer in UART. We can use it to send data in batches (instead of FIFO mode, only one byte can be sent, and each byte needs to wait for the buffer to be blank before sending the next byte ), this will increase the data transmission speed to a certain extent. The other is to avoid packet loss (this problem has not been realized yet ).

For usage, let's talk about the principle. The code is very simple and can be used in polling or interrupt mode.

1. In the round-robin mode, first we need to configure the relevant registers. I will not say much about this. I want everyone to know how to configure it. Then, we do not need to care about FIFO, as long as the FIFO buffer does not overflow. How to Query Overflow? Query ufstatn bit. Or bit [9 ]. You can pause when the data in the FIFO is full of 8 bytes (for a small delay, sending in the FIFO can avoid sending overflow, but it is not suitable for high-speed scenarios) with while (rufstat0 & 0x0010 ); it can be 9 bytes or 10 bytes. Of course, one byte is fine (1 byte doesn't seem very interesting, just like FIFO is useless ). I like to pause in the few bytes, but we need to consider the optimal transmission speed. The purpose of a brief pause is to avoid FIFO overflow. If you do not pause, data will overflow (write failure) and be lost.

2. In the interrupt mode, the FIFO principle is similar to round-robin. When the data in the FIFO is equal to the trigger byte set in ufcon, the request is interrupted, the transmission of all data is completed during the interruption. This also avoids FIFO overflow. When triggered, the service will be interrupted.

Void _ IRQ uart0_tx1_oint (void)
{
/* Determine whether the FIFO sending buffer is full or the string ends */
While (! (Rufstat0 & 0x200) & (* uart0txstr! = '/0') // If the buffer is full, exit the interrupt. If the trigger condition is met, that is, when the trigger byte is reached, the data volume in the FIFO is stabilized at a level, but it will not overflow (I am going to solve the problem, and I will not rule out understanding errors)
{
Rutxh0 = * uart0txstr ++;
For (I = 0; I <700; I ++); // delay to prevent FIFO write errors
}
Ri_ispc = bit_utxd0;
If (* uart0txstr = '/0 ')
{
Rintmsk | = bit_utxd0;
Ri_ispc = bit_utxd0;
}
}

When sending data in FIFO mode, if the round robin method is used (for non-high-speed scenarios, it is best to use the bdma or interrupt method in High-Speed scenarios, so the round robin method is rarely used), ensure that the accept of FIFO does not overflow, similar to the interrupt method, trigger conditions are set through software. For example, if (rufstat0 & 0x000f> 0x0008) triggers Reading 8 bytes of data in the FIFO. However, we also need to consider that the read receiving FIFO should not be empty, for example, while (rufstat0 & 0x000f)> 0x0000) {read receiving FIFO }. This round robin method is relatively stable and applicable to low speed. It is not recommended.

DIY