78.PL and PS share data interactively via Bram

The purpose of this article is to use block memory for PS and PL data interaction or data sharing, through the ZYNQ PS end of the master GP0 port to write data to Bram, and then through the PS end of the Mater GP1 the data read out, the results printed output to the serial terminal display. Involves the use of Axi BRAM Controller and IP such as Block memery generator.   This series of articles as far as possible to make each experiment is relatively independent, the process as far as possible to ensure integrity, to ensure the reproducibility of the experiment. However, the use of the module or IP specific role and usage is not guaranteed to repeat the detailed introduction.   The development board used in this article is the Miz702 (compatible Zedboard) PC development Environment version: the Vivado 2015.2 Xilinx SDK 2015.2  to implement the structure diagram: First, the construction of the PL-End hardware architecture  1.1 New Project  1.2 all the way Next, select zedboard 1.3 Create a new block design 1.4 Click Add IP, double-click zynq processing system 1.5 click Run Block Au Tomation, in the popup dialog box select ok 1.6 Double-click Zynq Module, under peripheral, keep UART0, all the rest remove  1.7 under Pl-ps configuration, select GP0 and GP1 and click OK After the  1.8 configuration is complete (this test does not use DDR and IO):  1.9 Click, add IP, adding two AXI BRAM controller 1.10 tips----Repeat IP module can be added in Tcl Way, You can change the name.  1.11 double-click the Axi BRAM Controller module (l two), change number of BRAM interfaces to 1 1.12 Click Add IP, add block Memory genera tor  1.13 Double-click Block memory Generator to change the memory Type.  1.14 Click Run connection  Automation to change the connection target of Axi_bram_ctrl_1 S_axi port to  1.15 Click Re-layout, the following is a good hardware framework 1.16 Click on Address Editor to see that the system has automatically assigned the correct address for us  1.17 right click on block design, click creater HDL Wrapper, this step to generate the entire hardware engineering of the top level module & nbsp;1.18 Click ok 1.19 Click Generate Output products, this step to the source of IP core load into the project (seemingly)  1.20 click generate 1.21 Click Generate bit, then you need to wait patiently  1.22 complete, you can select the information you want to see, you can also click cancel 1.23 click File, select Export hardware 1.24 Select the include bitstream, convenient in the SDK directly can burn the FPGA configuration file  1.25 Select   and then click OK, this hardware environment to build complete   Two, PS end software to achieve data sharing  2.1 Open the SDK interface as follows, the information here is hardware-related, for example, in the address Map This column can be seen Axi_bram_ctrl_0 and just under Vavado address editor addresses are consistent 2.2 new project 2.3 Enter the project name, click next2.4 Select Hello world,finish2.5 the src path, the code in the HELLOWORLD.C to modify the following

1#include <stdio.h>2#include"platform.h"3#include"xil_io.h"   //This header file contains important IO read-write functions4#include"Xparameters.h"  //in this header file, the hardware address mapping parameters are written as macro definitions for easy use5 6 //void print (char *str);7 8 intMain ()9 {Ten        intnum; One        intRev; A init_platform (); -  -xil_printf ("------The test is start ...------\n\r"); the  -  -     //Xpar_axi_bram_ctrl_0_s_axi_baseaddr is the address of axi_bram_ctrl_0, Xil_out32 writes data to BLK_MEM_GEN_0 by controlling axi_bram_ctrl_0  -      for(num=0; num< the; num++ ) +     { -Xil_out32 (xpar_axi_bram_ctrl_0_s_axi_baseaddr + num*4,0x10000000+num);// +     } A  at  -     //Xpar_axi_bram_ctrl_1_s_axi_baseaddr is the address of Axi_bram_ctrl_1, xil_in32 through the control of the AXI_BRAM_CTRL_0, the data in the BLK_MEM_GEN_0 read out  -     //PS and PL can share data in Blk_mem_gen_0 -     for(num=0; num< the; num++ ) -        { -Rev = Xil_in32 (xpar_axi_bram_ctrl_1_s_axi_baseaddr + num*4); inxil_printf ("The data at%x is%x \n\r", Xpar_axi_bram_ctrl_1_s_axi_baseaddr + num*4, rev.); -        } to  +xil_printf ("------The test is end!------\n\r"); -  the cleanup_platform (); *     return 0; $}

2.6 Set serial terminal 2.7 Burn bit file to FPGA 2.8 configuration software Burn Write file 2.9 configuration 2.10 configuration 2.11 Serial terminal print out information as follows:------The test is start ...------
The data at 80000000 is 10000000
The data at 80000004 is 10000001
The data at 80000008 is 10000002
The data at 8000000C is 10000003
The data at 80000010 is 10000004
The data at 80000014 is 10000005
The data at 80000018 is 10000006
The data at 8000001C is 10000007
The data at 80000020 is 10000008
The data at 80000024 is 10000009
The data at 80000028 is 1000000A
The data at 8000002C is 1000000B
The data at 80000030 is 1000000C
The data at 80000034 is 1000000D
The data at 80000038 are 1000000E------The test is end!------Three, summarizes this article through the PS end to write data to the PL end of the Bram, and then the data from the PL end read to the PS end, Thus, the data interaction and sharing between PL and PS can be realized simply.

78.PL and PS share data interactively via Bram