A simplified UART circuit design based on FPGA "reprint"

0 Introduction
With the widespread popularization and application of embedded system, UART (Universal asynchronous Receiver Transmiller) is widely used as a serial data transmission method. The UART allows full-duplex communication on a serial link. Serial Peripherals to Rs 232-c Asynchronous serial interface is typically implemented using a dedicated integrated circuit, the UART. Common serial interface chips such as 8250, 8251, NS16450, etc., can achieve a more comprehensive serial communication function. In the actual application, we often do not need such a complete function, which will result in the waste of resources and increase the cost. With the rapid development of EDA technology, we can integrate the required UART functions into the FPGA according to our own demand, thus simplifying the circuit, reducing the volume and improving the reliability of the system. Based on this idea, the author chooses Altera's Ep1c12q240cq8 in the design and uses the Verilog HDL design to realize the core function of the UART. 1 UART Communication principle serial communication is divided into two types: synchronous communication mode and asynchronous way of traffic. The UART is a universal asynchronous transmitter and is a serial asynchronous communication method. It is a key module for communication between various devices, allowing full-duplex communication on a serial link. On the transmitter side, the parallel digital signal needs to be converted into a serial signal to be wired or wireless to another device, and at the receiving end, the serial signal must be restored to a parallel signal for data processing. The UART is used to deal with this data and the serial string between and and string conversion.
The UART transmits a character starting with the start bit (start bit), ending with a stop bit (stop bit), and there is no fixed time interval between the characters. Each character is preceded by a starting bit (low level), the character itself consists of the 5~8 bit data bits, then a check digit (optional), and finally the stop bit (1-bit, 1-bit or 2-bit), and the stop bit is followed by an indefinite length of idle bit. Both the stop bit and the idle bit specify a high level so that a falling edge is guaranteed at the beginning of the start bit.

Figure 1 Data transfer format

2 implementation of UART in FPGA
Hardware circuit design of 2.1UART
The RS-232 interface standard is commonly used in serial communication. Hardware circuit is mainly composed of FPGA serial module, MAX3232 and DB-9, circuit diagram 2 shows. The data is entered from the Txd end of the DB-9, and after the level conversion by MAX3232, it is entered by the Rxd end of the FPGA serial module, and then the other modules are entered into the FPGA by the bus. Data processing through the data bus into the FPGA serial module, in which the string conversion by the Txd end output to the MAX3232, after the level of conversion by the rxd end of the DB-9 output.

Figure 2 UART hardware circuit diagram

1.2.2 UART Structure Design UART is mainly composed of the baud rate module, the transmission module, the receiving module, which consists of three parts.
2.2.1 Baud rate Occurrence module
When the UART is sending data, it is only possible to move the data serially at a certain rate. However, when the UART is receiving serial data, it is critical to move the data into the shift register at any time. Ideally, the serial data is sampled at the intermediate time of each bit of the serial data. For each bit of data segmentation, the more time the segment, the serial data sampling is closer to the midpoint, because the receiver and the sender of the clock can not be fully synchronized, the time of the more segmented, the receiver of the probability of sampling error is lower. But the more fragmented the time, the higher the sampling time, the greater the overhead of the system. Therefore, in the actual design, the clock frequency of 16 times times the baud rate is adopted. Each data width of the UART transceiver is 16 times times the clock period of the baud rate generator output. If you follow the 9600b/s to send and receive, then the baud rate generator output clock frequency should be 9600x16hz. Since the external clock is 25MHz, it is easy to write different values through the bus to the baud rate generator hold registers, and then use the counter to generate the desired baud rate. The calculation formula is: 25000000/(16x expected baud rate)-1.
2.2.2.2 Send module

The transmitting module mainly realizes the cache of the parallel data, and then the serial data is output in accordance with the established data frame format, and its mechanism 3 shows:

Figure 3 UART transmit Module

A) data_input[7:0] is a 8-bit parallel data input, converted to serial data from the TXD output;
b) WRN is write control signal, for 1 o'clock prohibit data input, when 0 is allowed to input;
c) reset to the system reset input, low-level active;
D) CLK is the system clock signal input, generated by the baud rate generator;
e) Tser is a token of the sequence conversion process: remains at 1 without data conversion and becomes 0 at the beginning of the string conversion.

and maintained at 0 during the conversion process, F) Tbre is a hallmark of the entire process. In the experiment, the serial data structure is 1 bit starting bit, 8 bits data bit, 1 bit parity bit, 1 bit stop bit. The transmission of the data is controlled by the external receiving module, the receiving module gives the WRN signal, and theUART transmitting module data-input the parallel data into the transmit buffer according to this signal, and then converts it through the shift register and adds the parity bit after the conversion, sends to the port TXD For serial output. During the whole work process, the output signal tbre as a sign signal, after the serial data all output is finished to 0, and when the sending module is not working, it remains 0.
2.4 Receiver Module
The receive module is shown in Structure 4. The function of the receiving module is to convert the received serial data into parallel data for output and to determine whether the received data is wrong. The internal structure and working process of the receiving module is similar to that of the transmitting module, except that the work of the receiving module and the sending module work in the opposite direction, which is the serial and conversion of the data.

Figure 4 UART receiver Module
A) RXD receive serial data input;
b) RDN is the input control end, only the RDN is 0 o'clock, the parallel data is allowed to output;
c) Data-ready is a sign that the data is ready;
D) Parity-error is the mark that the check digit is wrong;
e) Framing-error is a sign that the frame is wrong;
f) data-out[7:0] is the parallel data output terminal.

The receiving module starts from capturing to the first 0 of the data string, and then passes the 8 data bits that are subsequently entered sequentially through the shift to complete channeling and conversion in the register, and outputs the parallel data to Port Data-out. After the 8 data bits are shifted to the register, the receiving module detects whether the last digit of the input data string is 1 (stop bit) to determine if the received data frame is wrong, and if not 1, the output Framing-error 1.
3 simulation Verification in the experiment, the author chooses Altera company's Cyclone series of EP1C12Q240C8 chip, the hardware description language uses Verilog HDL, Quartus 5.1 for logic synthesis, the simulation tool uses ModelSim6.0. The simulation results for the transmit module and the receiving module are shown in 5 respectively. The data sent can be transmitted strictly in accordance with the serial communication Protocol, and the received data is completely correct. After the simulation test, the program is downloaded to the FPGA chip to run, the results of communication data is correct, the circuit is stable and reliable.

Figure 5 Transmit and receive module emulation

4 concluding remarks
The UART communication function is realized by FPGA , which can realize the receiving and transmitting of the data, and can judge the check bit and stop bit when the data is received, and can form a complete frame data format when sending the data. This paper uses FPGA design to realize the core function of UART, and can be used for asynchronous serial communication with host computer. The experiment proves that the UART design occupies less resources and is stable and reliable.
The author's innovative viewpoint: This paper analyzes the structure of UART system, and can realize the corresponding communication function according to the actual need, simplifies the circuit design , improves the system reliability, and can be embedded into each communication system flexibly.

A simplified UART circuit design based on FPGA "reprint"