Analog waveform AD5601 output based on small feet DDS FM amplitude modulated phase shift waveform

First of all, the matrix keyboard, the matrix keyboard column has a pull-down resistor, the default is 0000, the default line input is 1111, when there is a button pressed, the column input will be pulled high, then the output of the control line to do the scan, the keyboard with key_flag_r0 level as enable, here with Key_ Flag after shaking with the key value of the bitwise and, as the corresponding keys to determine the conditions.

Module Juzhen
(
Input CLK,
Input Rst_n,
input [3:0] Col_data,
Output reg [3:0] Row_data,
Output Key_flag,//the mark of key is pressed
Output reg [3:0] Key_value,

Output Reg KEY_FLAG_R0
);
Parameter Scan_idle = 3 ' b000;
Parameter scan_jitter= 3 ' b001;
Parameter scan_col0 = 3 ' b011;
Parameter scan_col1 = 3 ' b010;
Parameter scan_col2 = 3 ' b110;
Parameter scan_col3 = 3 ' b100;
Parameter Scan_read = 3 ' b101;
Parameter scan_jttter2= 3 ' b111;

reg [19:0] CNT;
reg [2:0] current_state;
reg [2:0] next_state;
Always @ (Posedge CLK or Negedge rst_n) begin
if (!rst_n) begin cnt<=0; End
Else
Begin
if (cnt>=20 ' h7ffff) begin Cnt<=0;end
else Cnt<=cnt+1;end
End
[Email protected] (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Current_state <= Scan_idle;
else if (cnt = = h7ffff) current_state <= next_state;
End
[Email protected]*
Begin Case (Current_state)
Scan_idle://init
if (col_data! = 4 ' b0000) next_state = Scan_jitter; Initialization
else Next_State = Scan_idle;
Scan_jitter://escape the Jitter
if (col_data! = 4 ' b0000) next_state = scan_col0;//de-jitter
else Next_State = Scan_idle;
Scan_col0://1th Row
if (col_data! = 4 ' b0000) Next_State = Scan_read;else Next_State = scan_col1;
Scan_col1://2th Row
if (col_data! = 4 ' b0000) Next_State = Scan_read;else Next_State = scan_col2;
Scan_col2://3th Row
if (col_data! = 4 ' b0000) Next_State = Scan_read;else Next_State = scan_col3;
Scan_col3://4th Row
if (col_data! = 4 ' b0000) Next_State = Scan_read;else Next_State = scan_idle;
Scan_read://lock the Vaule
if (col_data! = 4 ' b0000) Next_State = Scan_jttter2;else Next_State = scan_idle;
Scan_jttter2://when your Hand is gone
if (col_data! = 4 ' b0000) Next_State = Scan_jttter2;else Next_State = scan_idle;
Endcase
End
reg [3:0] col_data_r;
reg [3:0] row_data_r;

[Email protected] (Posedge CLK or Negedge rst_n)

Begin if (!rst_n) begin Row_data <= 4 ' b1111;key_flag_r0 <= 0;end
else if (cnt = = H7FFFF) begin
Case (Next_State)
Scan_idle:begin row_data <= 4 ' b1111;key_flag_r0 <= 0;end//scan_jitter:
Scan_col0:row_data <= 4 ' b0001;
Scan_col1:row_data <= 4 ' b0010;
Scan_col2:row_data <= 4 ' b0100;
Scan_col3:row_data <= 4 ' b1000;
Scan_read:begin
Row_data_r <= Row_data;
Col_data_r <= Col_data;
Key_flag_r0 <= 1;
End
Scan_jttter2:
Default:; Default Vaule
Endcase
End
End
Always @ (Posedge CLK or Negedge rst_n)
Begin if (!rst_n) key_value <= 0;
else if (cnt = = H7FFF)
Begin
if (key_flag_r0 = = 1 ' B1)//the mark of key is pressed
Begin
Case ({row_data_r,col_data_r})//row_data row, Col_data col
8 ' b0001_0001:key_value <= 4 ' D0;
8 ' b0010_0001:key_value <= 4 ' D1;
8 ' B0100_0001:key_value <= 4 ' D2;
8 ' B1000_0001:key_value <= 4 ' D3;
8 ' B0001_0010:key_value <= 4 ' d4;
8 ' B0010_0010:key_value <= 4 ' d5;
8 ' b0100_0010:key_value <= 4 ' d6;
8 ' B1000_0010:key_value <= 4 ' d7;
8 ' b0001_0100:key_value <= 4 ' d8;
8 ' b0010_0100:key_value <= 4 ' D9;
8 ' b0100_0100:key_value <= 4 ' D10;
8 ' b1000_0100:key_value <= 4 ' D11;
8 ' b0001_1000:key_value <= 4 ' D12;
8 ' b0010_1000:key_value <= 4 ' D13;
8 ' b0100_1000:key_value <= 4 ' D14;
8 ' b1000_1000:key_value <= 4 ' D15;
Default:key_value <= Key_value;
Endcase
End
Else
Key_value <= Key_value;
End
End
Capture The Falling Endge
Reg KEY_FLAG_R2,KEY_FLAG_R1;
[Email protected] (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
KEY_FLAG_R1 <= 0;
KEY_FLAG_R2 <= 0;
End
Else
Begin
Key_flag_r1 <= key_flag_r0;
KEY_FLAG_R2 <= key_flag_r1;
End
End
Assign Key_flag = key_flag_r2 & ~key_flag_r1; When your hand is gone
Endmodule

Amplitude phase waveform Selection Frequency control module

Module Ddsout
(
Output reg [7:0]data,
Input CS,
Output [3:0] row,
input [3:0]col,
Input SCLK,
Input Rst_n,
Input CLK
);

Wire [3:0] key_value;
Juzhen Xiaodou
(
. CLK (CLK),
. Rst_n (Rst_n),
. Col_data (COL),
. Row_data (Row),
. Key_flag (Key_flag),
. Key_value (Key_value)
);
reg [8:0] adress;
Reg[3:0]cnt1,cnt2;
[Email protected] (Posedge CLK or Negedge rst_n)
Begin

if (!rst_n) begin Cnt1<=1;end
else if (cnt1==15) cnt1<=1;
else if (key_value==2&key_flag==1) cnt1<=cnt1+1;

End
[Email protected] (Posedge CLK or Negedge rst_n)
Begin

if (!rst_n) begin Cnt2<=1;end
else if (cnt2==15) cnt2<=1;
else if (key_value==6&key_flag==1) cnt2<=cnt2+1;

End

reg [15:0] adress_r;
[Email protected] (Posedge sclk or Negedge rst_n)
Begin
if (!rst_n) adress_r<=0;
else adress_r<=adress_r+cnt1; Frequency Control word

End
Always @ (Posedge sclk)
if (!rst_n) adress<=0;
else if (adress>511) adress=0;
Else
adress<=adress_r[15:7]+cnt2; Phase Control Word

Wire [7:0]sina_data,san_data,fang_data,ju_data;
Sina Sina_ut
(
. Address (adress),
. Outclock (SCLK),
. Outclocken (CS),
. Reset (0),
. Q (Sina_data)
);

San San_ut
(
. Address (adress),
. Outclock (SCLK),
. Outclocken (CS),
. Reset (0),
. Q (San_data)
);
Fang Fang_ut
(
. Address (adress),
. Outclock (SCLK),
. Outclocken (CS),
. Reset (0),
. Q (Fang_data)
);
Ju Ju_ut
(
. Address (adress),
. Outclock (SCLK),
. Outclocken (CS),
. Reset (0),
. Q (Ju_data)
); ROM module call, can refer to the call of the great God Http://www.cnblogs.com/tony-ning/p/4971053.html

reg [1:0]cnt3;//Waveform selection
reg[1:0]cnt4;//amplitude Adjustment
[Email protected] (Posedge CLK or Negedge rst_n)
if (~rst_n) cnt3<=0;

else if (key_value==3&key_flag==1)
cnt3<=cnt3+1;
else if (cnt3>3) cnt3<=0;
else cnt3<=cnt3;
[Email protected] (Posedge CLK or Negedge rst_n)
if (!rst_n) cnt4<=0;
else if (key_value==7&key_flag==1)
cnt4<=cnt4+1;
else if (cnt4>3) cnt4<=0;
else cnt4<=cnt4;
reg [7:0]data_reg;

Always @ (CNT3)

if (! Rst_n) data_reg<=sina_data;
ELSE begin
Case (CNT3)
0:data_reg<=sina_data;
1:data_reg<=san_data;
2:data_reg<=fang_data;
3:data_reg<=ju_data;
default:data_reg<=sina_data;
Endcase
End

[Email protected] (Posedge SCLK)
if (!rst_n) Data=data_reg;
ELSE begin
Case (CNT4)
0:data=data_reg;
1:data=data_reg>>1;
2:data=data_reg>>2;
3:data=data_reg>>3;
Default:data=data_reg;
Endcase
End

Endmodule

DAC output module

Module ad5601spi//mode:cpol=1,cpha=0;
(
input [7:0] Q,
Input CLK,
Input Rst_n,
Output Reg SCLK,
Output REG CS,
Output Reg Sdin
);
reg [2:0] CNT;
Reg[5:0]state;
[Email protected] (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n) begin Cnt<=0;sclk<=1;end
else if (cnt==4) begin Cnt<=0;sclk<=1;end
else if (cnt<=2) begin Cnt<=cnt+1;sclk<=1;end
ELSE BEGIN Cnt<=cnt+1;sclk<=0;end
End
reg [15:0] data;

Always @ (Posedge CLK or Negedge rst_n)
if (!rst_n) begin state<=0; Cs=1;sdin=0;end
ELSE begin
Case (state)
0:begin if (cnt==1) begin cs<=0;data={2 ' b00,q[7:0],6 ' b000000};state<=state+1;end else begin state<=0;cs<= 1;end End
1:if (cnt==2) Begin Sdin<=data[15];state<=state+1;end
2:if (cnt==2) Begin Sdin<=data[14];state<=state+1;end
3:if (cnt==2) Begin Sdin<=data[13];state<=state+1;end
4:if (cnt==2) Begin Sdin<=data[12];state<=state+1;end
5:if (cnt==2) Begin Sdin<=data[11];state<=state+1;end
6:if (cnt==2) Begin Sdin<=data[10];state<=state+1;end
7:if (cnt==2) Begin Sdin<=data[9];state<=state+1;end
8:if (cnt==2) Begin Sdin<=data[8];state<=state+1;end
9:if (cnt==2) Begin Sdin<=data[7];state<=state+1;end
10:if (cnt==2) Begin Sdin<=data[6];state<=state+1;end
11:if (cnt==2) Begin Sdin<=data[5];state<=state+1;end
12:if (cnt==2) Begin Sdin<=data[4];state<=state+1;end
13:if (cnt==2) Begin Sdin<=data[3];state<=state+1;end
14:if (cnt==2) Begin Sdin<=data[2];state<=state+1;end
15:if (cnt==2) Begin Sdin<=data[1];state<=state+1;end
16:if (cnt==2) Begin Sdin<=data[0];state<=state+1;end
17:if (cnt==2) Begin State<=0;cs<=1;end
Endcase
End

ENDMODULE//SPI Falling Edge Prepare data AD5601 accept data

Analog waveform AD5601 output based on small feet DDS FM amplitude modulated phase shift waveform