Analysis of LCD Driver for YL-LCD35 Based on S3C2410

Reprinted please indicate the source

Author: Pony

There is a 2410 board on hand, LCD is a YL-LCD35. Write a driver analysis, make a technical note for yourself, for future reference.

 

For chips with On-Chip LCD controllers such as 2410, the most important thing to write an LCD driver is to configure the internal registers. 2410 supports two types of LCD: STN and TFT, and supports up to 24 BPP display.

 

 

The figure above is taken from 2410 datasheet. It is the internal diagram of the 2410lcd driver. It briefly describes the above modules.

Regbank is a register group. The registers that need to be manually configured by developers are included in this list. The following will be a detailed description.

Lcddma is the dedicated DMA for LCD drivers. With DMA, data can be directly exchanged with peripherals without occupying the CPU.

Tiemgen and lpc3600 are used to generate timing-related control signals.

Vidprcs is similar to a data buffer between lcddma and peripherals.

 

From this we can also see that 2410 of the drivers mainly do two things: one is to generate necessary timing control signals. 2. Generate video data signals. this is done by configuring the registers in regbank.

 

People who have worked on LCD driver development know that timing sequence is the most important for slow display devices like LCD. here I will mainly talk about the timing configuration. The other parameters such as data signal and address pointer are relatively simple. It is easy to understand datasheet. we will not describe it here. about the timing, specific to the YL-LCD35. there are several signals to introduce.

Vclk is a pixel clock signal and can be used as a LCD clock signal.

Vsync is a frame synchronization signal. That is to say, each time a pulse is sent, a new video signal starts to be transmitted.

Hsync is a line synchronization signal.

Vden data transmission enabling signal.

Lend line end signal

 

After having a preliminary understanding of the above signals, we can see the two figures below. the first figure is a typical sequence diagram of TFT liquid crystal. this figure is also taken from datasheet 2410, and the second figure is the timing diagram of the YL-LCD35 LCD.

 

 

 

 

 

Compare the two images. dotclk is equivalent to vclk. The second line of Figure 2 is marked with "1 horizon1_period", which is equivalent to hsync of figure 1. Similarly, we can obtain the correspondence between other signals. in Figure 1, vbpd, vfpd, and vspw signals are the return time, which is reserved to be compatible with the previous CRT Display (similar to hsync ). configuring these signals is equivalent to configuring vsync. vclk is determined by the hckl and lcdcon1 registers. the specific formula is as follows:

Vclk = hclk/[(clkval + 1) '2]

The following code is provided from the youlong Development Board. It intercepts the register configuration of the above signal. The other part is not related to the timing. I will not describe it here.

# Define vbpd_320240 (4) // The back shoulder of the Vertical Synchronous signal # define vfpd_320240 (4) // The front shoulder of the Vertical Synchronous signal # define vspw_320240 (4) // pulse width of the Vertical Synchronous signal # define hbpd_320240 (13) // The back shoulder of the horizontal synchronous signal # define hfpd_320240 (4) // The front shoulder of the horizontal synchronous signal # define hspw_320240 (18) // pulse width rlcdcon1 = (clkval_tft_320240 <8) | (0 <7) | (3 <5) | (12 <1) | 0; rlcdcon2 = (vbpd_320240 <24) | (Bytes <14) | (vfpd_320240 <6) | (vspw_320240); rlcdcon3 = (hbpd_320240 <19) | (hozval_tft_320240 <8) | (hfpd_320240); rlcdcon4 = (13 <8) | (hspw_320240); rlcdcon5 = (1 <11) | (1 <10) | (1 <9) | (1 <8) | (0 <7) | (0 <6) | (1 <3) | (bswp <1) | (hwswp );