ARM compilation: ldr,str,ldm,stm, pseudo-instruction Ldr

Ldr,str,ldm,stm's naming laws:

The naming of these instructions seems to be hard to remember, now look for patterns.

Instructions	Sample	Effect	Inductive name interpretation
LDR rd,addressing	LDR R1,[r0]	Addressing to Rd [mem to Reg]	Load to register
STR rd,addressing	STR R1,[R0]	Rd ro addressing [reg to Mem]	Store Register
LDM Rn,reglist	LDMFD SP!,{R0-R7,PC}	*sp to Reglist[mem to Reg]	Load to Reglist
STM Rn,reglist	STMFD SP!,{R0-R7,LR}	Reglist to *sp[reg to Mem]	Store Reglist
Therefore, the name of the ldr,str,ldm,stm is the Reg register as the main body, LD represents the load load register, ST represents the store save register. The source of the load, the place to save is memory.

LDR is also a pseudo-directive, at this time the inevitable shape is: LDR Reg, =expr. Expr can be a 32-bit immediate number, or it can be a label.

Ldr means a wide range of address reading instructions, and reads the address value based on the relative offset of the PC.

The ADR reads pseudo-directives for a small range of addresses and reads the address values based on the relative offset of the PC into the registers. ADR Register,exper

can be used for program jumps or to find data in a data pool.

ADR r0,disptab   ; Load conversion table address to r0.; Disptab compiled is a fixed address, the address of the space after the storage of n units of data. After the program runs up the address and the compiled address are different. This command loads the run-time address. LDRB R1,[R0,R2]  ; reads the data in the conversion table into R1, with the value of R2 as the offset. .... Disptab DCB 0xc0,0xf9,0xa4,0xb0

ADLR reads pseudo-directives for the middle range address, which is larger than the range of addresses that an ADR can read.

;=================;Memory Control;=================Bwscon EQU 0x48000000;Bus width & wait statusBANKCON0 EQU 0x48000004;Boot ROM ControlBANKCON1 EQU 0x48000008;BANK1 ControlBANKCON2 EQU 0x4800000c;BANK2 ControlBANKCON3 EQU 0x48000010;BANK3 ControlBANKCON4 EQU 0x48000014;BANK4 ControlBANKCON5 EQU 0x48000018;BANK5 ControlBANKCON6 EQU 0x4800001c;BANK6 ControlBANKCON7 EQU 0x48000020;BANK7 ControlREFRESH EQU 0x48000024;Dram/sdram RefreshBanksize EQU 0x48000028;Flexible Bank SizeMRSRB6 EQU 0x4800002c;Mode Register set for SDRAM Bank6MRSRB7 EQU 0x48000030;Mode Register set for SDRAM Bank7
; To set the Mem control register, a total of 13.;*******************************************
; ; in Init.s

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Setmemcontroller

ADRL r0, Smrdata ldr R1,=bwscon;Bwscon Address    AddR2, R0, # the    ;End Address of Smrdata0LDR R3, [R0], #4    ;unsigned int *pvalue = (unsigned int*) smrdata; R3 = pvalue[0], pvalue+=1;    StrR3, [R1], #4    ;unsigned int *reg_addr = (unsigned int*) Bwscon; *REG_ADDR = R3; Reg_addr+=1;    CMPR2, R0;if (pValue! = smrdata+52) {loop};bne%b0
; End ofSetmemcontroller

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Ltorgsmrdata DATA;Memory configuration should is optimized for best performance;The following parameter is not optimized.;Memory Access cycle parameter strategy;1) The memory settings is safe parameters even at Hclk=75mhz.;2) SDRAM refresh period is for Hclk<=75mhz.DCD (0+ (b1_bwscon<<4) + (b2_bwscon<<8) + (b3_bwscon<< A) + (b4_bwscon<< -) + (b5_bwscon<< -) + (b6_bwscon<< -) + (b7_bwscon<< -) DCD ((b0_tacs<< -) + (b0_tcos<< One) + (b0_tacc<<8) + (b0_tcoh<<6) + (b0_tah<<4) + (b0_tacp<<2) + (B0_PMC));GCS0DCD ((b1_tacs<< -) + (b1_tcos<< One) + (b1_tacc<<8) + (b1_tcoh<<6) + (b1_tah<<4) + (b1_tacp<<2) + (B1_PMC));GCS1DCD ((b2_tacs<< -) + (b2_tcos<< One) + (b2_tacc<<8) + (b2_tcoh<<6) + (b2_tah<<4) + (b2_tacp<<2) + (B2_PMC));GCS2DCD ((b3_tacs<< -) + (b3_tcos<< One) + (b3_tacc<<8) + (b3_tcoh<<6) + (b3_tah<<4) + (b3_tacp<<2) + (B3_PMC));GCS3DCD ((b4_tacs<< -) + (b4_tcos<< One) + (b4_tacc<<8) + (b4_tcoh<<6) + (b4_tah<<4) + (b4_tacp<<2) + (B4_PMC));GCS4DCD ((b5_tacs<< -) + (b5_tcos<< One) + (b5_tacc<<8) + (b5_tcoh<<6) + (b5_tah<<4) + (b5_tacp<<2) + (B5_PMC));GCS5DCD ((b6_mt<< the) + (b6_trcd<<2) + (B6_scan));GCS6DCD ((b7_mt<< the) + (b7_trcd<<2) + (B7_scan));GCS7DCD ((refen<< at) + (trefmd<< A) + (trp<< -) + (tsrc<< -) + (tchr<< -) +refcnt) DCD 0x32;SCLK power Saving mode, Banksize 128m/128mDCD 0x20;MRSR6 CL=2CLKDCD 0x20;MRSR7 CL=2CLK

; mem sets the data pool for parameter values. Total 13*4bytes.
;*********************************************************

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ARM compilation: ldr,str,ldm,stm, pseudo-instruction Ldr