Arm chip address re ing (easy to understand)

Ing means a one-to-one correspondence. Re- ing is the one-to-one relationship of re-allocation.

We can regard the memory as a black box with the output and input ports. As shown in, the input is the address, and the output is the data stored on the corresponding address. Of course, this black box is made available by complicated semiconductor circuits. We do not care about the specific implementation method. The storage unit is generally byte. In this way, each byte storage unit corresponds to an address. When a valid address is input from the address bus of the storage, the data stored on the storage unit corresponding to this address will appear on the Data Bus.

Figure 1

Common Single-Chip Microcomputer stores executable code and data in the memory. The CPU in the single chip microcomputer obtains the instruction code and data from the memory. Each physical storage unit in the memory corresponds to its address one by one and is immutable. 1. The CPU reads the stored unit on the 0x00000000 address.

Figure 2

Arm is complicated. The difference between an ARM chip and an ordinary single-chip microcomputer in terms of memory address is that the address of some physical storage units in the ARM chip can be changed according to the settings. That is to say, a physical storage unit now corresponds to an address. After setting, the storage unit corresponds to another address. Figure 3 shows a random example (not matching the ARM chip) to describe the address re ing process. Figure 3 maps the storage unit on the 0x00000000 address to the new address 0x00000007. CPU access 0x00000007 is the physical storage unit that accesses 0x00000000.

Figure 3

Figure 4: Figure 5 shows two address re ing methods for the ARM chip. Figure 3 suppose that our application is stored in the extended Flash, then the abnormal vector table of the application is stored in 64 at the beginning of 0x80000000 (32 of them store the exception vector) physical storage unit. However, after an ARM core exception (Interruption) occurs, it starts from 0x00000000 ~ 0x0000003f obtains the exception vector from the address range. Therefore, 0x80000000 ~ The storage units in the 0x8000003f range are remapped to 0x00000000 ~ 0x0000003f address range. CPU access 0x00000000 to later ~ 0x0000003f is used to access 0x80000000 ~ The storage unit in the range of 0x8000003f. Figure 4 only shows the address re ing of the first abnormal vector. The address re ing of the entire abnormal vector table is equivalent to this process.

Figure 4

Figure 5 shows another ARM chip ing method. This ing can be decided by the user or not (the relevant code is provided by a third party in startup. s of the project file, and can be modified by the user ). This ing is mainly used to increase the speed of application exceptions. When we store the application in-chip Flash, the abnormal vector table is stored in 0x00000000 ~ 0x0000003f storage unit. Each time an exception occurs, the CPU usage ranges from 0x00000000 ~ 0x0000003f returns the exception vector. However, the access speed to ram is much higher than the access speed to flash, So we adopt the following method to improve the abnormal speed:

(1) Replace 0x00000000 ~ Copy the abnormal vector table in the flash storage unit to x40000000 ~ 0x4000003f (the lowest-end 64-byte storage unit of In-disk RAM.

(2) Change 0x40000000 ~ The address of the storage unit in the 0x4000003f range is remapped to 0x00000000 ~ 0x0000003f address range.

Figure 5

After this is done, when an exception occurs, the CPU takes the exception vector from the abnormal vector area in the ram area, which is faster. For example, when a reset is interrupted, the CPU takes the command from the address 0x00000000. However, because the address has been re-mapped, The 0x00000000 is converted to 0x40000000 by the address converter, the CPU is actually the instruction (exception vector) in the memory unit 0x400000000 In the ram zone ).

Of course, you can skip this ing. 0x00000000 ~ The 0x0000003f storage unit has the same abnormal vector table. However, if this process is not performed, the exception may be slower. However, there are many situations where the difference in speed is unnecessary.

The address converter in the figure is controlled by the control register menmap. You can set menmap to control address re ing. This address converter is implemented through an internal hardware circuit.