Based on s3c2440a + SDRAM (k4m000063)

Source: Internet
Author: User

The system uses two pieces of K4M51163-BG75 of SDRAM, the size is 2*64 m.

1. How SDRAM works

1.1 SDRAM Overview

SDRAM: synchronous dynamic random access memory, synchronous dynamic random memory. Synchronization means that the clock frequency (CLK) is the same as the CPU's AHB Bus clock frequency (hclk), and internal commands are sent to Data Transmission Based on it; dynamic means that the storage array needs to be constantly refreshed to ensure that data is not lost. Random means that the index data is not stored in a linear order, but the data can be read and written by freely specified addresses.

1.2 concepts related to SDRAM

(1) Bank

An SDRAM chip is generally composed of four banks and is part of the K4M51163-BG75 function diagram.

The middle visible K4M51163-BG75 has 4 banks, a bank size is 8 m * 16 bite, 8 M indicates that the Bank has 8 m storage units, and each unit can store 16 bit of data. The basic storage unit of SDRAM is the storage unit, and the smallest storage unit is bit.

(2) Bit Width

As mentioned above, a storage unit contains 16 bits. This is the bit width of the bank and the Bit Width of an SDRAM chip. The bit width indicates each transmission cycle (here it refers to a cycle of the clock sent to the CLK end) the amount of data transmitted (16 bits ).

(3) Amount of SDRAM

The amount of SDRAM is the number of storage units. The formula is as follows:

Amount of SDRAM = number of banks * (number of rows * Number of columns)

Here, the number of banks is 4, while the number of rows and the number of columns are described in

The number of rows can be a0 ~ A12 represents a total of 13 address lines. The number of lines that can be expressed reaches the 13 power of 2 (8192); the number of columns is a0 ~ A9 is represented by a total of 10 address lines. The number of columns that can be expressed reaches the 10 power of 2 (1024). At the same time, the travel and column address lines are reused in time.

The internal structure of the SDRAM is a storage array. The array is the same as the table. Like the table retrieval principle, a row is specified first, and then a column is specified, in this way, we can accurately find the required cells, which is the basic principle of the SDRAM chip addressing. For memory, this cell is called a storage unit. What is the name of this table (storage array? It is the bank. Our system is using two pieces of K4M51163-BG75, so how does the two pieces of K4M51163-BG75 work? See

You can use nscs0 to select which SDRAM chip is currently working. After you select a specific SDRAM chip, you can use ba0 and BA1 to select a specific bank, select a specific row, and then select a column to find a specific storage unit.

Note: SDRAM transmits data of one storage unit at a time, that is, 16-bit data, through dq0 ~ Dq15 reads or writes data. The reading here is the discharge of the storage capacitor, and the writing is the charging of the storage capacitor. each bit of data is stored in the storage capacitor, that is, a high or low level that can be expressed by one person is helpful to understand this point.

2 K4M51163PG-BG75

Pins of 2.1 SDRAM

To work with SDRAM, it is necessary to have a connection with the memory controller. At the same time, for an electrical component, power supply is also essential, and data transmission requires a clock to synchronize data transmission. Therefore, the power supply and clock pins are required. What control pins are needed?

I: First, we know that the memory controller must first determine which of the two SDRAM chips the system uses before addressing the selected chip. Therefore, we need to have a chip selection signal, which selects an SDRAM chip at a time.

II: The next step is to address the selected chips in the bank. Currently, the number of banks in the SDRAM is up to four, so the addresses of the two banks are required.

III: The row and column (storage unit) addressing of the selected bank. The number of address lines required is designed based on the size and organizational structure of the SDRAM chip, but under the same capacity, the number of rows remains unchanged, and only the number of columns changes according to the bit width. The larger the bit width, the smaller the number of columns, because the storage units required are reduced.

IV: after finding a storage unit, you must read or write the data of this unit. Therefore, you must have a data I/O channel with the same bit width, therefore, there must be a corresponding number of data leads.

2.1 functional diagram of the K4M51163PG-BG75

2.2 K4M51163PG-BG75 pins

The following figure shows the pins.

These pins are described in detail below

CLK

System clock: The SDRAM clock pin of the mobile controller of s3c2443 connects to this pin. This clock pin is used for synchronous data transmission and serves as a trigger reference for data transmission. Shows the requirements of the K4M51163PG-BG75 for CLK cycle time

Combined

While s3c2443 uses hclk to provide clock signals for the SDRAM chip, see

Our system hclk = 400 MHz/3 = 133 MHz, so we should go to CAS latency = 3 to know the requirement for a CLK cycle time is> = 7.5ns, with hclk = 133 MHz, we can calculate a clock cycle time of hclk = 1/133 MHz = 7.5188ns> 7.5ns. We can see that the current hclk can provide a CLK that satisfies the K4M51163PG-BG7.

/CS

Chip selection signal, used when multiple SDRAM chips are used, used to select a specific time when the SDRAM chip works, and the s3c2443 nscs0 is connected to this pin, the mobie controller controls this signal line to choose any of our systems using two pieces of SDRAM.

Cke

The valid clock signal line is connected to the scke of s3c2443. The mobile controller uses this signal line to make the CLK valid.

A0 ~ A12

Line address line, used to select the row of each bank, that is, row activation.

A0 ~ A9

The column address line is used to select the columns of each bank, that is, the storage cell is selected, and the row and column address are reused.

Ba0 ~ BA1

Select the address of the bank. Because the SDRAM chip has four banks, you need two Bank address lines to select the four banks.

/RAS

Select the line address. When the signal line is low, the address line is a0 ~ The specific row address sent by A12 has actual significance, that is, the Specific Row address can be selected.

/CAS

Column address selection. When the signal line is low, the address line is a0 ~ The specific column address sent by A9 has practical significance, that is, you can select a specific column and store cells.

/We

Write enabling: data can be read during high-power periods. data can be written during low-power periods.

L (u) dqm

Data input/output shielding is used during burst transmission.

Dq0 ~ 15

Data input/output

2.3 internal basic operations and working sequence of SDRAM

2.3.1 SDRAM chip Initialization

After power-on, the SDRAM must be initialized before other operations can be performed on it. The initialization procedure is as follows:

(1) After power-on, SDRAM must wait for at least us, and at least one empty operation command must be executed after the wait time is over.

(2) After executing a pre-charging command, execute an empty Operation Command. These two operations will pre-charge all storage units, so that all devices in the array are in the STANDBY state.

(3) SDRAM must execute at least two self-Refresh commands. After each refresh command, an empty Operation Command is executed. These operations can refresh the internal of the sdram chip and bring the counters to normal operation, so that SDRAM can prepare for mode register programming.

(4) execute the Mrs (mode register set) command to initialize the mode register (mode register ).

After callback is in normal Mrs mode, you can execute an emrs (Extended Mode register) command to implement the desired operation mode.

Is the operation requirement after K4M51163PG-BG75 power-on

The following figure shows a rough description of the SDRAM initialization process.

2.3.2 The SDRAM row is valid.

After initialization, to address the storage unit in a bank, you must first determine the row, that is, the row is selected to make it active, and then confirm the column. We know that to determine the row, first we need to select the chip and the Bank address, the two actions and the row can be selected at the same time, is the K4M51163PG-BG75 of the bank and the row selected truth table, also real-time sequence diagram

It can be seen that, at the same time as/CS and bank addressing,/RAS (row address selection) is also in a valid state (low level valid). At this time, a0 ~ The A12 address line sends a Specific Row address. There are 13 address lines in total. Because they are in binary notation, there are 8192 rows (2 ^ 13 = 8192), a0 ~ Different binary values of A12 determine the specific ideas row address. Because the row is valid and the corresponding bank is valid, the row is also known as the bank. According to this table, it can also be converted to a sequence chart similar to the following, the figure below will enhance your understanding in this regard.

It can be seen that the column addressing signal and the reading command are sent at the same time. Although the column address line is shared with the row addressing, the CAS (column address strobe, column address selected) signals can distinguish between the operation and column addressing, and then use a0 ~ A9 to determine the specific column address. Note that the level change of RAS and CAs can be converted to a time sequence diagram similar to the following when the line is valid and the column addressing command is used.

We know that there must be an interval between the send-column READ command and the line-effective command. This interval is defined as trcd, that is, Ras to CAS delay (RAS to CAS delay ), it can also be understood as the row-based switching cycle, which is determined by the response time of the electronic components of the chip storage array (from one State to another, is the requirement of the K4M51163PG-BG75 for this parameter

Trcd is an important time series parameter of SDRAM. In the broad sense, trcd is measured in units of clock cycles. For example, if trcd is set to 2, the delay period is the two clock cycles, it depends on the clock frequency CLK (that is, the hclk sent from s3c2440a). It can be seen that trcd must meet the requirement of trcd> = 22.5ns. It is known that hclk = 400/3 MHz, A clock cycle time of hclk can be calculated = 1/133 MHz = 7.5188ns, so the trcd time requirement is at least three clock, according to the description of bankconn in the memory controller of s3c2440a

It can be seen that as long as the bankconn [3: 2] bit is equal to 01 or 10, it can meet the requirements of trcd and help to understand trcd.

After selecting the column address, you have determined the specific storage unit. The next thing is that the data passes through the data I/O channel (dq0 ~ Dq15) output to the memory bus (sdata0 ~ Sdata31, two pieces of SDRAM. However, after CAS is issued, it takes some time for data to be output. The time from CAS and read command to the first data output is defined as Cl (CAS latency, CAS latency ). Since Cl only appears during read, CL becomes the read latency (RL, read latency ). The unit of Cl is the same as that of trcd, which is the number of clock cycles. The specific time consumed is determined by the clock frequency. Cl is an important parameter of SDRAM. If this parameter is set incorrectly, it is very likely that the eboot of bootloader cannot update NK, I plan to write another article to share my problems and solutions. Next, let's take a look at the CL settings in the mrsr OF THE s3c2440a register.

We can see that the CL value should be 3, because our hclk = 133 MHz, so the register mrsr [] = 011.

Note that CAs are not delivered to the storage unit after the CL cycle. In fact, CAS and Ras arrive instantly at the same time, But CAS response time is faster. Why? Now we use 16 bits for the SDRAM chip, and the number of columns is 1024 (2 ^ 10). Then, we need to select a line address (that is, select all the storage bodies in a row, here, a storage unit has 16 storage bodies) 16*1024 storage bodies, and a column address value needs to select 16 storage bodies. However, the response time of the transistor in the storage body will still cause that the data cannot be triggered on the same rising edge as the CAS, And it is sure to delay at least one clock cycle.

Due to the size of the chip, the capacity of the capacitor in the storage unit is very small, so the signal must be amplified to ensure its effective identification. This amplification/driver is operated by the sense amp, A storage body corresponds to a sens amp channel.

See

However, the sense amp must have a preparation time to ensure the signal transmission strength (voltage comparison must be performed beforehand to determine the logic level ), therefore, a clock rising edge before data output on the data I/O bus begins, and the data has been transferred to the sense amp, that is, the data has been triggered at this time, after a certain amount of driving time, the data is finally transmitted to the data I/O bus for output. This time is called TAC (access time from CLK, access time after Clock triggering ). The unit of TAC is ns. different frequencies are clearly defined, but they must be smaller than one clock cycle. Otherwise, the efficiency will be reduced because the access time is too long. The K4M51163PG-BG75 defines this parameter as tsac,

The minimum clock cycle of the K4M51163PG-BG75 is 7.5ns, and the maximum value of tsac is 6ns, which is less than 7.5ns. It should be emphasized that each data is read with TACs, including in the continuous reading, but the TACs of the second data are started at the same time of the first data transmission. Facilitate understanding of TAC Parameters

The CL value cannot exceed the design specifications of the chip. Otherwise, the memory may be unstable, the NK cannot be updated, and the system cannot be started normally, and it cannot be changed temporarily before Data Reading. Set the CL cycle in the Mrs phase during startup initialization.

2.5 data input (write)

The data write operation is performed after trcd, but no Cl is available at this time (Remember, CL only appears in the read operation). The real value table for data input and output

As shown in the figure, the only difference between data input and data output is that the/we signal is valid (low-level) during data input ). The data signal is sent by the SDRAM Controller. When the input is made, it only needs to be directly transmitted to the data input register (data input register), and then the write driver needs to charge the storage capacitor, therefore, data can be sent at the same time as CAS, that is, the write latency is 0. However, the data is not written into the storage capacitor in real time, because it takes some time to select a pass transistor (just like when reading) and charge the capacitor, therefore, real Data Writing takes a certain period.

2.6 burst length

Burst refers to the continuous data transmission of adjacent storage units in the same row. The number of storage units (columns) involved in continuous transmission is the burst length (burst lengths, (BL) is the description of the BL type and length in s3c2440a.

It can be seen that the memory controller of s3c2440a only supports the BT type of sequential, and only supports the burst length of 1 byte, is the BT type and length supported by the K4M51163PG-BG75

We can see that in a3 = 0 and a0 ~ When A2 is 1, the supported burst length is full page. Full page burst transmission refers to all the storage units (2 ^ 10 = 1024) in a row in the bank) from the beginning to the end for continuous transmission, but this page definition for the chip is narrow, we commonly use pages in a broad sense, we know that each transmission of the memory system is in the unit of a SDRAM chip Bit Width (16 bit width of the K4M51163PG-BG75), and our system is using two pieces of K4M51163PG-BG75. The Bank address and row address obtained by each SDRAM chip are the same for each addressing. In this way, the full page operation is equivalent to reading/writing to all the storage units in the same bank in the memory system, 2*2 ^ 10 = 2048 storage units. This is the page in a broad sense.

In the burst transmission technology, as long as the actual column address and the burst length are specified, the memory will automatically read/write the corresponding number of storage units at a time without the need for the memory controller to provide the column address continuously. In this way, except that the first data transmission requires several cycles (mainly the previous delay, which is generally TRC + Cl), each subsequent data can only be obtained in one cycle, helps you understand the highlights of transmission

2.7 pre-Charging

Because the addressing of SDRAM is dedicated, after reading and writing operations, if you want to address another row in the same bank, you must disable the row that is valid (working, resend the row/column address. The bank closes the existing work line. The operation to open a new line is precharge ). Pre-charging can be controlled through commands, or through auxiliary settings, so that the SDRAM will be automatically pre-charged after each read/write operation. In fact, pre-charging is a type of data Rewriting for all the storage bodies in the working row, resetting the row address, and releasing the sense-Amp. It is a diagram of the pre-Charging Control truth table.

It can be seen that the address line A10 controls whether to automatically pre-charge the current bank after reading and writing, which is the "Auxiliary Settings" mentioned above ". In a separate pre-charging command, A10 controls whether to pre-charge the specified bank or all banks. The former requires the Bank address, the latter only needs to set the A10 signal to a high level.

After the pre-charge command is issued, it takes some time to allow the send of the RAS line valid command to open a new working line. This interval is called TRP (precharge command period, pre-charge effective period ). Like trcd and Cl, the unit of TRP is also the number of clock periods. For the K4M51163PG-BG75, see

The minimum TPR value is 22.5ns. For details about the memory controller of s3c2440a, see

To meet TPR> = 22.5ns, and each clock cycle is 7.5ns, at least three clock, as long as the TRP bit value is 01 or 10, TPR meeting the requirements can be provided to the SDRAM chip.

2.8 refresh

The reason for becoming a SDRAM is that it requires constant refresh to retain the data. Therefore, it is the most important operation of SDRAM. The refresh operation is the same as the refresh operation in the pre-Charging mode. It uses the sense-AMP to read and then write. But why should we refresh the pre-charging operation? Because the pre-charge operation is performed on one or all banks and is performed irregularly, the refresh operation has a fixed cycle and is performed on all rows in sequence, to retain the data in the storage bodies that have not been overwritten for a long time. However, unlike the pre-charging of all banks, the rows here refer to the rows with the same addresses in all banks, and the working row addresses in the pre-charging banks are not necessarily the same.

So how long does it take to refresh again? Currently, it is recognized that the maximum effective storage period of capacitor data in the storage body is 64 ms, that is, the cycle of each row refreshing is 64 ms. The refresh speed is: the number of rows/64 ms.

The K4M51163PG-BG75 describes this parameter, as shown in.

The 8 K here is actually 8192 (2 ^ 13), and the 8 K represents the number of rows per bank in the chip. The refresh command is valid for one row. The sending interval also varies with the total number of rows. The 64 ms/8192 = 7.8125us value is used for 80192 rows.

There are two types of refresh operations: auto refresh (AR) and Self refresh (SR ). No matter what the refresh method is, you do not need to provide the line address information externally, because this is an internal automatic operation. For Ar, there is a row address generator (also called the refresh timer) inside the SDRAM to automatically generate the row address in sequence. Because refresh is performed on all the buckets in a row, column addressing is not required, or CAS is valid before Ras. Therefore, AR, also known as CBR (CAS before Ras, is refreshed by column positioning in advance. Since refresh involves all banks, all banks stop working during the refresh process, and the time occupied by each refresh varies with the values of different SDRAM chips, the K4M51163PG-BG75 describes this parameter, as shown in:

We can see that in the 11 (80ns/7.5ns = 10) clock period, all the work instructions can only wait and cannot be executed. We know that each 7.8125us sends a line refresh command, that is to say, in the 1041 (7.8125us/7.5ns) clock cycle, 11 clock cycles are used to wait for a row to refresh.

Sr is mainly used for data storage in sleep mode with low power consumption. The most famous application in this regard is STR (suspend to ram, sleep hangs in the memory ). When an AR command is issued, placing cke in an invalid state enters Sr mode, which is a description of the K4M51163PG-BG75

It can be seen that after the AR command is issued, if cke is set to a level (invalid), it enters the SR mode and no longer relies on the system clock, instead, refresh the system based on the internal clock, which is closely related to the application when the system goes to sleep, and further summarizes the system when it goes to sleep. All external signals except cke during SR are invalid (no refresh command is required ).

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